Integrated circuit including memory having reduced cross talk

1. An integrated circuit comprising:

a first electrode;

a second electrode;

a first resistivity changing material contacting the first electrode at a first interface;

a second resistivity changing material contacting the second electrode at a second interface; and

a resistivity changing material extending between the first resistivity changing material and the second resistivity changing material;

wherein the first interface is spaced apart from the second interface by a lateral distance, and

wherein a direct communication path between the first interface and the second interface is greater than the lateral distance.

2. The integrated circuit of claim 1 , wherein the direct communication path comprises at least one of a thermal communication path and an electrical communication path.

3. The integrated circuit of claim 1 , wherein a first direction is defined by the lateral spacing of the first interface and the second interface,

wherein a second direction is defined substantially perpendicular to the first direction, and

wherein the first interface and the second interface are offset with respect to the second direction.

4. The integrated circuit of claim 3 , wherein the offset is greater than a thickness of the resistivity changing material.

5. The integrated circuit of claim 3 , wherein the resistivity changing material forms a plate of resistivity changing material.

6. The integrated circuit of claim 1 , wherein:

the resistivity changing material extending between the first resistivity changing material and the second resistivity changing material contains

a barrier structure within the resistivity changing material.

7. The integrated circuit of claim 6 , wherein the barrier material has a lower thermal conductivity than the resistivity changing material.

8. The integrated circuit of claim 6 , wherein the barrier material comprises one of SiO 2 , porous SiO 2 , aerogel, xerogel, SiN, and a low-k dielectric.

9. The integrated circuit of claim 1 , wherein the resistivity changing material comprises a phase change material.

10. A memory comprising:

a first electrode;

a second electrode; and

a resistivity changing material extending from a first interface at the first electrode to a second interface at the second electrode,

wherein the first interface is spaced apart from the second interface by a lateral distance, and

wherein a distance between the first interface and the second interface through the resistivity changing material is greater than the lateral distance.

11. The memory of claim 10 , further comprising:

a barrier structure within the resistivity changing material.

12. The memory of claim 11 , wherein a material of the barrier structure has a lower thermal conductivity than the resistivity changing material.

13. The memory of claim 11 , wherein the material of the barrier structure comprises one of SiO 2 , porous SiO 2 , aerogel, xerogel, SiN, and a low-k dielectric.

14. The memory of claim 10 , wherein a first direction is defined by the lateral spacing of the first interface and the second interface,

wherein a second direction is defined substantially perpendicular to the first direction,

wherein the first interface and the second interface are offset with respect to the second direction.

15. The integrated circuit of claim 14 , wherein the offset is greater than a thickness of the resistivity changing material.

16. The memory of claim 10 , wherein the resistivity changing material comprises a phase change material.

17. A system comprising:

a host; and

a memory device communicatively coupled to the host, the memory device comprising:

a first electrode;

a second electrode; and

a resistivity changing material extending from a first interface at the first electrode to a second interface at the second electrode,

wherein the first interface is spaced apart from the second interface by a lateral distance, and

wherein the distance between the first interface and the second interface through the resistivity changing material is greater than the lateral distance.

18. The system of claim 17 , further comprising:

a barrier structure within the resistivity changing material.

19. The system of claim 17 , wherein a first direction is defined by the lateral spacing of the first interface and the second interface,

wherein a second direction is defined substantially perpendicular to the first direction, and

wherein the first interface and the second interface are offset with respect to the second direction.

20. The system of claim 17 , wherein the memory device further comprises:

a write circuit configured to program a storage location at the first interface and a storage location at the second interface;

a sense circuit configured to read the storage location at the first interface and the storage location at the second interface; and

a controller configured to control the write circuit and the sense circuit.

21. A method for fabricating an integrated circuit, the method comprising:

providing a substrate including a first electrode, a second electrode, and isolation material between the first electrode and the second electrode;

depositing a barrier material over the first electrode, the second electrode, and the isolation material;

removing a portion of the barrier material to expose the first electrode and the second electrode; and

depositing a resistivity changing material over the first electrode, the second electrode, and the barrier material.

22. The method of claim 21 , further comprising:

depositing an etch stop material over the substrate; and

removing a portion of the etch stop material to expose the first electrode and the second electrode.