IP Library Granted Patent US 7,994,536
Granted Patent B2
US 7,994,536 · App. 12/033,533 · Granted Aug 9, 2011

Integrated circuit including U-shaped access device

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Quick Facts
Patent No.
US 7,994,536
App. No.
12/033,533
Granted
Aug 9, 2011
Kind
B2
Abstract

An integrated circuit includes a U-shaped access device and a first line coupled to a first side of the access device. The integrated circuit includes a contact coupled to a second side of the access device and self-aligned dielectric material isolating the first line from the contact.

Claims (91)

1. An integrated circuit comprising:

a U-shaped access device;

a first line coupled to a first side of the access device;

a contact coupled to a second side of the access device; and

self-aligned dielectric material isolating the first line from the contact.

2. The integrated circuit of claim 1 , wherein the access device is provided in a substrate, the access device comprising:

a doped first region having a first polarity;

a doped second region having a second polarity opposite the first polarity, the second region isolated from the first region by the dielectric material; and

a doped third region having the first polarity, a top of the third region contacting a bottom of the first region and a bottom of the second region.

3. The integrated circuit of claim 1 , wherein the access device comprises one of a diode and a bipolar transistor.

4. The integrated circuit of claim 1 , further comprising:

a resistance changing memory element, a first side of the memory element coupled to the contact; and

a second line coupled to a second side of the memory element.

5. The integrated circuit of claim 1 , further comprising:

a first silicon layer coupling the first line to the access device.

6. The integrated circuit of claim 2 , wherein the substrate includes a doped fourth region having the second polarity, a top of the fourth region contacting a bottom of the third region.

7. The integrated circuit of claim 2 , wherein the substrate comprises a silicon on insulator structure including an insulating material layer, a top of the insulating material layer contacting a bottom of the third region.

8. The integrated circuit of claim 4 , wherein the memory element and the contact are self-aligned to the second line.

9. The integrated circuit of claim 4 , wherein the memory element comprises a phase change element.

10. The integrated circuit of claim 5 , further comprising:

a second silicon layer coupling the contact to the access device.

11. A system comprising:

a host; and

a memory device communicatively coupled to the host, the memory device comprising:

a U-shaped access device;

a first metal line coupled to a first side of the access device;

a metal contact coupled to a second side of the access device; and

a phase change element, a first side of the phase change element coupled to the metal contact.

12. The system of claim 11 , wherein the access device is provided in a substrate, the access device comprising:

a heavily doped first region having a first polarity;

a heavily doped second region having a second polarity opposite the first polarity, the second region isolated from the first region; and

a lightly doped third region having the first polarity, a top of the third region contacting a bottom of the first region and a bottom of the second region.

13. The system of claim 11 , wherein the access device comprises one of a diode and a bipolar transistor.

14. The system of claim 11 , wherein the memory device further comprises:

a metal bit line coupled to a second side of the phase change element,

wherein the first metal line comprises a word line.

15. The system of claim 14 , wherein the phase change element and the contact are self-aligned to the bit line.

16. A method for fabricating an integrated circuit, the method comprising:

fabricating a U-shaped access device in a substrate;

fabricating a first line coupled to a first side of the access device;

fabricating a contact coupled to a second side of the access device; and

fabricating a resistive memory element having a first side coupled to the contact.

17. The method of claim 16 , wherein fabricating the access device comprises fabricating a diode in a silicon on insulator structure.

18. The method of claim 16 , wherein fabricating the access device comprises fabricating a bipolar transistor in a silicon substrate.

19. The method of claim 16 , further comprising:

fabricating a second line coupled to a second side of the phase change element.

20. The method of claim 16 , wherein fabricating the access device comprises:

providing the substrate including an active area and isolation regions, the active area including a first region having a first polarity;

depositing a doped first silicon layer over the substrate, the first silicon layer having the first polarity;

depositing an electrically conductive material layer over the first silicon layer;

depositing a nitride layer over the electrically conductive material layer;

etching a portion of the nitride layer and the electrically conductive material layer to provide an opening exposing a portion of the first silicon layer;

nitridizing the exposed portion of the first silicon layer to provide a nitridation layer;

damaging a portion of the nitridation layer;

oxidizing the damaged portion of the nitridation layer and the underlying portion of the first silicon layer to provide a first oxide layer;

removing an undamaged portion of the nitridation layer;

depositing a second silicon layer over exposed portions of the first silicon layer, the nitride layer, and the first oxide layer;

depositing a second oxide layer over the second silicon layer in the opening;

etching exposed portions of the second silicon layer and underlying portions of the first silicon layer and the active area to provide a first trench having a first depth and to expose a portion of the first oxide layer;

etching the exposed portion of the first oxide layer and underlying portions of the first silicon layer and the active area to provide a second trench having a second depth less than the first depth;

filling the first trench and the second trench with a dielectric material;

removing the second oxide layer, the second silicon layer, and the first oxide layer to expose a portion of the first silicon layer;

doping the exposed portion of the first silicon layer to provide a doped third silicon layer having a second polarity opposite the first polarity; and

annealing the first and third silicon layers to diffuse dopants into a portion of the first region to provide the access device.

21. The method of claim 16 , wherein fabricating the access device comprises:

providing the substrate including an active area and isolation regions, the active area including a first region having a first polarity;

depositing a doped first silicon layer over the substrate, the first silicon layer having the first polarity;

depositing an electrically conductive material layer over the first silicon layer;

depositing a first nitride layer over the electrically conductive material layer;

etching a portion of the first nitride layer and the electrically conductive material layer to provide an opening exposing a portion of the first silicon layer;

nitridizing the exposed portion of the first silicon layer to provide a nitridation layer;

damaging a portion of the nitridation layer;

oxidizing the damaged portion of the nitridation layer and the underlying portion of the first silicon layer to provide a first oxide layer;

removing an undamaged portion of the nitridation layer;

depositing a second silicon layer over exposed portions of the first silicon layer, the first nitride layer, and the first oxide layer;

depositing a second oxide layer over the second silicon layer in the opening;

etching exposed portions of the second silicon layer and underlying portions of the first silicon layer and the active area to provide a first trench in the substrate having a first depth and to expose a portion of the first oxide layer;

etching the exposed portion of the first oxide layer and underlying portions of the first silicon layer and the active area to provide a second trench in the substrate having a second depth less than the first depth;

filling the first trench and the second trench with a dielectric material;

removing the second oxide layer;

depositing a second nitride layer over exposed portions of the first nitride layer, the dielectric material, the second silicon layer, the first oxide layer, and the first silicon layer;

spacer etching the second nitride layer to expose the second silicon layer;

removing the second silicon layer, the first oxide layer, and the underlying portion of the first silicon layer to expose the substrate;

heavily doping the exposed substrate to provide a doped second region in the substrate having a second polarity opposite the first polarity; and

annealing the first silicon layer to diffuse dopants into the substrate to provide a doped third region in the substrate having the first polarity.

22. The method of claim 20 , wherein damaging the portion of the nitridation layer comprises implanting the portion of the nitridation layer using an angled implantation.

23. The method of claim 20 , wherein fabricating the access device further comprises:

oxidizing exposed portions of the first silicon layer, the second silicon layer, and the active area after etching to provide the second trench.

24. The method of claim 21 , wherein damaging the portion of the nitridation layer comprises implanting the portion of the nitridation layer using an angled implantation.

25. The method of claim 21 , wherein fabricating the access device further comprises:

oxidizing exposed portions of the first silicon layer, the second silicon layer, and the active area after etching to provide the second trench.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036575/0670 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2008
From: WEIS, ROLF; HAPP, THOMAS
To: QIMONDA AG
Reel/Frame 020528/0259 →