Memory system with extended memory density capability

1. A system comprising:

a central processing unit;

a first memory channel coupling the central processing unit to a first semiconductor memory unit, wherein the first memory channel is clocked with a first clock frequency; and

a second memory channel coupling the central processing unit to a second semiconductor memory unit, wherein the second memory channel is clocked with a second clock frequency smaller than the first clock frequency, the second memory channel being separate from the first memory channel,

wherein a databus width of the first memory channel is identical to a databus width of the second memory channel, and

wherein the first and second memory units are configured to be capable of storing independent data, and

wherein the first memory channel is directly coupled to a memory controller being integrated into the central processing unit and wherein the second memory channel is indirectly coupled to the memory controller via a buffer chip external to the central processing unit.

2. The system according to claim 1 , wherein the first and second memory units are of the same memory hierarchy level.

3. The system according to claim 1 , wherein the first memory unit does not store data as a copy of data stored in the second semiconductor memory unit.

4. The system according to claim 1 , wherein the first memory channel comprises one or more first memory module sockets configured to establish a connection to the first semiconductor memory unit, and wherein the second memory channel comprises one or more second memory module sockets configured to establish a connection to the second semiconductor memory unit.

5. The system according to claim 4 , wherein a number of the first memory module sockets is smaller than a number of second memory module sockets.

6. The system according to claim 1 , wherein the first and the second memory units are comprised by first and second DRAM dual in-line memory modules.

7. The system according to claim 1 , wherein the central processing unit comprises an integrated circuit serving as a memory controller, the memory controller having a first data interface coupled to the first memory channel and a second data interface coupled to the second memory channel.

8. The system according to claim 1 , wherein the first memory channel is directly coupled to the central processing unit via a memory controller integrated into the central processing unit, and wherein the second memory channel is coupled to the central processing unit via a memory controller external to the central processing unit.

9. The system according to claim 8 , wherein the second memory channel is coupled to the external memory controller via a buffer chip.

10. The system according to claim 1 , wherein the first semiconductor memory unit is placed on a same substrate as the central processing unit.

11. The system according to claim 1 , wherein the first semiconductor memory unit is placed on a same substrate as a memory controller.

12. A system comprising:

a central processing unit;

a first memory channel coupling the central processing unit to first DRAM memory units belonging to a first memory hierarchy level, wherein the first memory channel is clocked with a first clock frequency; and

a second memory channel, separate from the first memory channel the central processing unit to second DRAM memory units also belonging to the first memory hierarchy level, wherein the second memory channel is clocked with a second clock frequency smaller than the first clock frequency, and

wherein the first memory hierarchy level denotes memory belonging to a main memory of the system, and wherein a databus width of the first memory channel is identical to a databus width of the second memory channel,

wherein one of the first memory channel and the second memory channel is directly coupled to a memory controller being integrated into the central processing unit and wherein the other of the first memory channel and the second memory channel is indirectly coupled to the memory controller via a buffer chip external to the central processing unit.

13. The system according to claim 12 , wherein the first memory channel comprises one or more first memory module sockets configured to establish a connection to the first DRAM memory unit, and wherein the second memory channel comprises one or more second memory module sockets configured to establish a connection to the second DRAM memory unit.

14. The system according to claim 13 , wherein a number of the first memory module sockets is smaller than a number of second memory module sockets.

15. The system according to claim 12 , wherein the first DRAM memory unit is comprised by a first DRAM dual in-line memory module and the second DRAM memory unit is comprised by a second DRAM dual in-line memory module.

16. The system according to claim 12 , wherein the central processing unit comprises an integrated circuit serving as a memory controller, the memory controller having a first data interface coupled to the first memory channel and a second data interface coupled to the second memory channel.

17. The system according to claim 12 , wherein the first memory channel is directly coupled to the central processing unit via a memory controller integrated into the central processing unit, and wherein the second memory channel is coupled to the central processing unit via a memory controller external to the central processing unit.

18. The system according to claim 17 , wherein the second memory channel is coupled to the external memory controller via a buffer chip.

19. The system according to claim 12 , wherein the first DRAM memory unit is placed on a same substrate as the central processing unit.

20. The system according to claim 12 , wherein the first memory unit is placed on a same substrate as a memory controller.

21. An apparatus comprising:

means for processing data;

means for coupling the means for processing data to a first semiconductor memory unit via a first means for transporting data;

means for clocking the first means for transporting data with a first clock frequency;

means for coupling the means for processing data to a second semiconductor memory unit via a second means for transporting data, wherein the second means for transporting data is separate from the first means for transporting data;

means for clocking the second means for transporting data with a second clock frequency smaller than the first clock frequency, and

wherein a databus width of the first means for transporting data is identical to a databus width of the second means for transporting data and

wherein the first means for transporting data is directly coupled to a memory controller being integrated into the means for processing data and wherein the second means for transporting data is indirectly coupled to the means for processing data via a buffer chip external to the means for processing data.

22. A method comprising:

coupling a central processing unit to a first semiconductor memory unit via a first memory channel, wherein the first memory channel is clocked with a first clock frequency; and

coupling the central processing unit to a second semiconductor memory unit via a second memory channel that is separate from the first memory channel, wherein the second memory channel is clocked with a second clock frequency smaller than the first clock frequency, and

wherein a databus width of the first memory channel is identical to a databus width of the second memory channel and

wherein the first memory channel is directly coupled to a memory controller being integrated into the central processing unit and wherein the second memory channel is indirectly coupled to the memory controller via a buffer chip external to the central processing unit.