Integrated circuit to identify read disturb condition in memory cell

1. A method of operating a resistivity changing memory cell, comprising:

reading a resistivity changing sensor memory cell with a read operation that is different than a read operation associate with the resistivity changing memory cell;

identifying a read disturb condition associated with the resistivity changing memory cell if the different read operation caused a disturbance of data in the read resistivity changing sensor memory cell; and

performing a refresh operation in response to the identified read disturb condition.

2. The method of claim 1 , wherein identifying the read disturb condition comprises detecting a thermal condition associated with the resistivity changing memory cell that increases a probability of a read operation causing a disruption of data in the resistivity changing memory cell.

3. A method of operating a phase change memory array, comprising:

sensing a read disturb condition; and

performing a refresh operation when the read disturb condition is sensed,

wherein sensing the read disturb condition comprises:

programming a read disturb phase change memory cell to the reset state;

performing a read disturb read operation on the read disturb phase change memory cell with a read operation that is different than a read operation associated with a phase change memory cell; and

determining whether the read disturb condition exists based on whether the read disturb operation caused the read disturb phase change memory cell to have a resistance lower than a predetermined value.

4. The method of claim 3 , wherein performing a read disturb read operation comprising applying a voltage or current pulse to the read disturb phase change memory cell that is greater than a voltage or current pulse applied to phase change memory cells in the array in a read operation.

5. The method of claim 3 , wherein the read disturb condition is sensed at a time associated with each read cycle of the phase change memory array.

6. The method of claim 3 , wherein performing the refresh operation comprises:

reading data from each phase change memory cell in a portion of the phase change memory array; and

writing the read data back into each phase change memory cell, respectively.

7. The method of claim 6 , wherein the data is read from each phase change memory cell in the entire phase change memory array.

8. A method of operating a multi-bit phase change memory array, comprising:

sensing a read disturb condition associated with one of the multiple available states of a multi-bit phase change memory cell; and

performing a refresh operation when the read disturb condition is sensed;

wherein sensing a read disturb condition includes reading a phase change sensor memory cell with a read operation that is different than a read operation associate with the multi-bit phase change memory cell, and sensing the read disturb condition if the different read operation caused a disturbance of data in the phase change sensor memory cell.

9. The method of claim 8 , wherein the read disturb condition is associated with an intermediate state of the multi-bit phase change memory cell that lies between the set state and the reset state.

10. The method of claim 9 , wherein the intermediate state comprises one of a plurality of available intermediate states that is most susceptible to an inadvertent change of state due to a read operation performed thereon.

11. The method of claim 8 , wherein performing the refresh operation comprises:

reading data from each multi-bit phase change memory cell in a portion of the multi-bit phase change memory array; and

writing the read data back into each multi-bit phase change memory cell, respectively.

12. The method of claim 11 , wherein the data is read from each multi-bit phase change memory cell in the entire multi-bit phase change memory array.

13. An integrated circuit, comprising:

a resistivity changing memory cell; and

a read disturb system configured to identify a read disturb condition and perform a refresh operation on the memory cell in response thereto,

wherein the read disturb system is configured to identify the read disturb condition by reading a resistivity changing sensor memory cell with a read operation that is different than a read operation associated with the resistivity changing memory cell, and identifying the read disturb condition if the different read condition caused a disturbance of data in the read resistivity changing sensor memory cell.

14. The integrated circuit of claim 13 , wherein the read disturb system is configured to identify the read disturb condition by detecting a thermal condition associated with the memory cell.

15. A phase change memory system, comprising:

an array of phase change memory cells;

a phase change memory read sensor;

a refresh controller configured to perform a refresh operation on the array of phase change memory cells when the read sensor indicates a read disturb condition; and

a pulse generator configured to generate and provide a read disturb signal to the phase change memory read sensor.

16. The phase change memory system of claim 15 , wherein the phase change memory read sensor comprises a phase change memory cell, and wherein the read disturb signal causes a change in resistance of the phase change memory read sensor when the read disturb condition exists.

17. The phase change memory system of claim 15 , wherein the pulse generator is further configured to generate a reset pulse signal to force the phase change memory read sensor to a reset state.

18. A phase change memory system, comprising:

an array of phase change memory cells;

a phase change memory read sensor;

a refresh controller configured to perform a refresh operation on the array of phase change memory cells when the read sensor indicates a read disturb condition; and

a sense amplifier configured to sense a state of the phase change memory read sensor during a read operation, and communicate the sensed state to the refresh controller.

19. The phase change memory system of claim 15 , wherein the phase change memory cells comprise multi-bit phase change memory cells.

20. The phase change memory system of claim 19 , wherein the phase change memory read sensor comprises a multi-bit phase change memory cell.

21. The phase change memory system of claim 20 , wherein the read sensor is initially set to an intermediate state lying between a set state and a reset state, and wherein a read disturb condition is indicated when the intermediate state leaves a predetermined resistance range.

22. A phase change memory system, comprising:

an array of phase change memory cells; and

means for detecting a read disturb condition associated with the array and performing a refresh operation in response thereto,

the means for detecting further comprising:

means for reading a resistively changing sensor memory cell with a read operation that is different than a read operation associated with the resistively changing memory cell, and

means for identifying the read disturb condition if the different read condition caused a disturbance of data in the read resistively changing sensor memory cell.

23. The phase change memory system of claim 22 , wherein the detecting means further comprises read disturb sensor means for detecting the read disturb condition.