Method and apparatus for performing internal hidden refreshes while latching read/write commands, address and data information for later operation

1. A method of operating a system including a memory device, comprising:

upon receiving a request for an internal hidden refresh for the memory device:

latching external command, address, and data information for the memory device;

placing the memory device in a standby state;

during the standby state, performing the internal hidden refresh;

after performing the internal hidden refresh, placing the memory device in a state corresponding to the latched external command, address, and data information for the memory device; and

upon determining that the external command, address, and data information has changed after the received request for the internal hidden refresh, latching the changed external command, address, and data information.

2. The method of claim 1 , wherein the state corresponding to the latched external command is a write state.

3. The method of claim 1 , wherein placing the memory device in the state corresponding to the latched external command, address, and data information comprises providing the latched external command to a command decoder for the memory device.

4. The method of claim 1 , wherein placing the memory device in the state corresponding to the latched external command, address, and data information comprises providing the latched external address to an address buffer for the memory device.

5. The method of claim 1 , wherein placing the memory device in the state corresponding to the latched external command, address, and data information comprises providing the latched data to read/write data lines for the memory device.

6. A method of operating a system including a memory device, comprising:

upon receiving a request for an internal hidden refresh for the memory device:

latching external command, address, and data information for the memory device;

placing the memory device in a standby state;

during the standby state, performing the internal hidden refresh;

after performing the internal hidden refresh, placing the memory device in a state corresponding to the latched external command, address, and data information for the memory device; and

upon determining that the external command, address, and data information has changed within a predefined listening period beginning from the received request for the internal hidden refresh, latching the changed external command, address, and data information.

7. A memory device comprising:

circuitry configured to, upon receiving a request for an internal hidden refresh for the memory device:

latch external command, address, and data information for the memory device;

place the memory device in a standby state;

during the standby state, perform the internal hidden refresh;

after performing the internal hidden refresh, place the memory device in a state corresponding to the latched external command, address, and data information for the memory device; and

upon determining that the external command, address, and data information has changed after the received request for the internal hidden refresh, latch the changed external command, address, and data information.

8. The memory device of claim 7 , wherein the state corresponding to the latched external command is a write state.

9. The memory device of claim 7 , wherein placing the memory device in the state corresponding to the latched external command, address, and data information comprises providing the latched external command to a command decoder for the memory device.

10. The memory device of claim 7 , wherein placing the memory device in the state corresponding to the latched external command, address, and data information comprises providing the latched external address to an address buffer for the memory device.

11. The memory device of claim 7 , wherein placing the memory device in the state corresponding to the latched external command, address, and data information comprises providing the latched data to read/write data lines for the memory device.

12. A memory device comprising:

circuitry configured to, upon receiving a request for an internal hidden refresh for the memory device:

latch external command, address, and data information for the memory device;

place the memory device in a standby state;

during the standby state, perform the internal hidden refresh;

after performing the internal hidden refresh, place the memory device in a state corresponding to the latched external command, address, and data information for the memory device; and

upon determining that the external command, address, and data information has changed within a predefined listening period beginning from the received request for the internal hidden refresh, latch the changed external command, address, and data information.

13. A method for operating a system including a memory device, comprising:

determining an external selection time for the memory device;

upon determining that the external selection time for the memory device is less than a predetermined selection time, providing a first minimum selection time for the memory device, wherein at least one internal hidden refresh is performed during the first minimum selection time;

upon determining that the external selection time for the memory device is greater than or equal to the predetermined selection time, providing a second minimum selection time for the memory device, wherein at least a first and a second internal hidden refresh are performed during the second minimum selection time and wherein the second minimum selection time is greater than the first minimum selection time;

during the second minimum selection time and upon receiving a request for the second internal hidden refresh:

latching external command, address, and data information for the memory device;

placing the memory device in a standby state;

during the standby state, performing the second internal hidden refresh; and

after performing the second internal hidden refresh, placing the memory device in a state corresponding to the latched external command, address, and data information for the memory device.

14. The method of claim 13 , further comprising:

after latching the external command, address, and data information, determining whether the external command, address, and data information has changed;

upon determining that the external command, address, and data information has changed, latching the changed external command, address, and data information; and

placing the memory device in a state corresponding to the changed external command, address, and data information.

15. The method of claim 13 , wherein the second minimum selection time is maintained by the memory device only when the memory device is placed in a low-frequency mode.

16. The method of claim 13 , wherein each internal hidden refresh is performed in response to an internal timer of the memory device, and wherein an address for each internal hidden refresh is provided by an internal address counter of the memory device.

17. The method of claim 13 , wherein both read and write accesses are allowed during the first minimum selection time and the second minimum selection time.

18. The method of claim 13 , wherein the external selection time for the memory device is measured beginning at a first transition of a chip select signal.

19. The method of claim 13 , wherein external access to the memory module is restricted while the second internal hidden refresh is performed.

20. A memory device, comprising:

circuitry configured to:

determine an external selection time for the memory device;

upon determining that the external selection time for the memory device is less than a predetermined selection time, provide a first minimum selection time for the memory device, wherein at least one internal hidden refresh is performed during the first minimum selection time;

upon determining that the external selection time for the memory device is greater than or equal to the predetermined selection time, provide a second minimum selection time for the memory device, wherein at least a first and a second internal hidden refresh are performed during the second minimum selection time and wherein the second minimum selection time is greater than the first minimum selection time;

during the second minimum selection time and upon receiving a request for the second internal hidden refresh:

latch external command, address, and data information for the memory device;

place the memory device in a standby state;

during the standby state, perform the second internal hidden refresh; and

after performing the second internal hidden refresh, place the memory device in a state corresponding to the latched external command, address, and data information for the memory device.

21. The memory device of claim 20 , further comprising:

after latching the external command, address, and data information, determining whether the external command, address, and data information has changed;

upon determining that the external command, address, and data information has changed, latching the changed external command, address, and data information; and

placing the memory device in a state corresponding to the changed external command, address, and data information.

22. The method of claim 13 , wherein the second minimum selection time is maintained by the memory device only when the memory device is placed in a low-frequency mode.

23. The method of claim 13 , wherein each internal hidden refresh is performed in response to an internal timer of the memory device, and wherein an address for each internal hidden refresh is provided by an internal address counter of the memory device.

24. The memory device of claim 20 , wherein both read and write accesses are allowed during the first minimum selection time and the second minimum selection time.

25. The memory device of claim 20 , wherein the external selection time for the memory device is measured beginning at a first transition of a chip select signal.

26. The memory device of claim 20 , wherein external access to the memory module is restricted while the second internal hidden refresh is performed.

27. A system, comprising:

a memory controller; and

a memory device configured to:

determine an external selection time for the memory device, wherein the memory controller selects the memory device during the external selection time;

upon determining that the external selection time for the memory device is less than a predetermined selection time, provide a first minimum selection time for the memory device, wherein at least one internal hidden refresh is performed during the first minimum selection time and wherein the memory controller maintains the memory device in a selected state for the first minimum selection time;

upon determining that the external selection time for the memory device is greater than or equal to the predetermined selection time, provide a second minimum selection time for the memory device, wherein at least a first and a second internal hidden refresh are performed during the second minimum selection time, wherein the memory controller maintains the memory device in a selected state for the second minimum selection time, and wherein the second minimum selection time is greater than the first minimum selection time;

during the second minimum selection time and upon receiving a request for the second internal hidden refresh:

latch external command, address, and data information for the memory device;

place the memory device in a standby state;

during the standby state, perform the second internal hidden refresh; and

after performing the second internal hidden refresh, place the memory device in a state corresponding to the latched external command, address, and data information for the memory device.

28. The system of claim 27 , further comprising:

after latching the external command, address, and data information, determining whether the external command, address, and data information has changed;

upon determining that the external command, address, and data information has changed, latching the changed external command, address, and data information; and

placing the memory device in a state corresponding to the changed external command, address, and data information.

29. The system of claim 27 , wherein the second minimum selection time is maintained by the memory device only when the memory device is placed in a low-frequency mode.

30. The system of claim 27 , wherein each internal hidden refresh is performed in response to an internal timer of the memory device, and wherein an address for each internal hidden refresh is provided by an internal address counter of the memory device.

31. The system of claim 27 , wherein both read and write accesses are allowed during the first minimum selection time and the second minimum selection time.

32. The system of claim 27 , wherein the external selection time for the memory device is measured beginning at a first transition of a chip select signal.

33. The system of claim 27 , wherein external access to the memory module is restricted while the second internal hidden refresh is performed.