INTEGRATED CIRCUIT INCLUDING CONTACT CONTACTING BOTTOM AND SIDEWALL OF ELECTRODE

1 . An integrated circuit comprising:

a first electrode;

a second electrode;

resistivity changing material between the first electrode and the second electrode; and

a contact contacting a bottom and a first sidewall portion of the first electrode.

2 . The integrated circuit of claim 1 , wherein the first sidewall portion of the first electrode is tapered.

3 . The integrated circuit of claim 1 , wherein the first electrode comprises a ring electrode.

4 . The integrated circuit of claim 1 , wherein the first electrode has a sublithographic cross-section.

5 . The integrated circuit of claim 1 , further comprising:

a spacer defining a second sidewall portion of the first electrode.

6 . The integrated circuit of claim 1 , wherein the resistivity changing material comprises phase change material.

7 . A system comprising:

a host; and

a memory device communicatively coupled to the host, the memory device comprising:

a first electrode;

a second electrode;

phase change material between the first electrode and the second electrode; and

a contact contacting a bottom and a first sidewall portion of the first electrode.

8 . The system of claim 7 , wherein the first sidewall portion of the first electrode is tapered.

9 . The system of claim 7 , wherein the first electrode comprises a ring electrode.

10 . The system of claim 7 , wherein the first electrode has a sublithographic cross-section.

11 . The system of claim 7 , wherein the memory device further comprises:

a spacer defining a second sidewall portion of the first electrode.

12 . The system of claim 7 , wherein the memory device further comprises:

a write circuit configured to program the phase change material;

a sense circuit configured to read a state of the phase change material; and

a controller configured to control the write circuit and the sense circuit.

13 . A memory comprising:

a first electrode;

a second electrode;

means for storing data between the first electrode and the second electrode; and

a contact,

wherein the first electrode is recessed into the contact.

14 . The memory of claim 13 , further comprising:

means for accessing the means for storing data.

15 . The memory of claim 13 , wherein the recess is greater than 10% of a diameter of the first electrode.

16 . The memory of claim 13 , wherein the recess is greater than 50% of a diameter of the first electrode.

17 . The memory of claim 13 , wherein the first electrode comprises a ring electrode.

18 . The memory of claim 13 , wherein a cross-sectional width of the means for storing data is greater than a cross-sectional width of the first electrode.

19 . A method for fabricating an integrated circuit having a memory cell, the method comprising:

providing a preprocessed wafer including a contact and dielectric material over the contact, the dielectric material including a first opening exposing a portion of the contact;

etching the exposed portion of the contact to provide a second opening within the contact;

depositing electrode material within the second opening and the first opening to provide a first electrode;

fabricating a storage location coupled to the first electrode; and

fabricating a second electrode coupled to the storage location.

20 . The method of claim 19 , wherein etching the exposed portion of the contact to provide the second opening comprises etching the exposed portion of the contact to provide a tapered second opening within the contact.

21 . The method of claim 19 , wherein depositing electrode material within the second opening and the first opening to provide the first electrode comprises conformally depositing electrode material within the second opening and the first opening to provide a ring electrode.

22 . The method of claim 19 , wherein fabricating the storage location comprises fabricating a phase change material storage location.

23 . A method for fabricating a memory cell, the method comprising:

providing a preprocessed wafer including a first contact;

depositing a first dielectric material layer over the preprocessed wafer;

etching a first opening in the first dielectric material layer to expose the first contact;

conformally depositing a spacer material layer over exposed portions of the etched first dielectric material layer and the preprocessed wafer;

etching the spacer material layer to expose a portion of the first contact and to provide spacers on sidewalls of the first opening;

etching the exposed portion of the first contact self-aligned to the spacers to provide a second opening within the first contact;

depositing electrode material over exposed portions of the etched first dielectric material layer, the spacers, and the first contact;

planarizing the electrode material to expose the etched first dielectric material layer and the spacers to provide a first electrode;

fabricating a phase change material storage location coupled to the first electrode; and

fabricating a second electrode coupled to the storage location.

24 . The method of claim 23 , wherein etching the exposed portion of the first contact to provide the second opening comprises etching the exposed portion of the first contact to provide a tapered second opening within the first contact.

25 . The method of claim 23 , wherein depositing electrode material comprises conformally depositing electrode material, the method further comprising:

depositing a second dielectric material layer over the electrode material,

wherein planarizing comprises planarizing the second dielectric material layer and the electrode material to expose the etched first dielectric material layer and the spacers to provide a first ring electrode.

26 . The method of claim 23 , further comprising:

fabricating a second contact coupled to the second electrode.