Memory Data Bus Placement and Control

1 . A memory device, comprising:

a plurality of memory banks, wherein at least two of the memory banks share the same bus;

logic coupled to the memory banks via the different buses and operable to control access to the memory banks; and

a bi-directional tri-state buffer interposed between adjacent memory banks along the same bus so that each bus is segmented into a plurality of sections, each bus section being coupled to one or more different ones of the memory banks.

2 . The memory device of claim 1 , wherein the memory banks are arranged in a plurality of rows or columns and each bi-directional tri-state buffer is interposed between adjacent ones of the memory banks arranged in the same row or column.

3 . The memory device of claim 1 , wherein the logic is operable to:

determine which bank is to be accessed during a memory operation; and

activate each bi-directional tri-state buffer interposed between the logic and the bank to be accessed along the bus that couples the bank to the logic.

4 . The memory device of claim 3 , wherein the memory operation is a read operation and the logic is operable to activate read driver circuitry included in each bi-directional tri-state buffer interposed between the logic and the bank to be accessed during the read operation along the bus that couples the bank to the logic.

5 . The memory device of claim 3 , wherein the memory operation is a write operation and the logic is operable to activate write driver circuitry included in each bi-directional tri-state buffer interposed between the logic and the bank to be accessed during the write operation along the bus that couples the bank to the logic.

6 . The memory device of claim 3 , wherein the logic is operable to deactivate each bi-directional tri-state buffer disposed further from the logic than the bank to be accessed along the bus that couples the logic to the bank to be accessed.

7 . A method of fabricating a memory device, comprising:

disposing a plurality of memory banks on a substrate, wherein at least two of the memory banks share the same bus;

coupling logic to the memory banks via the different buses, wherein the logic is operable to control access to the memory banks; and

interposing a bi-directional tri-state buffer between adjacent memory banks along the same bus so that each bus is segmented into a plurality of sections, each bus section being coupled to one or more different ones of the memory banks.

8 . The method of claim 7 , wherein the memory banks are arranged in a plurality of rows or columns on the substrate and wherein interposing a bi-directional tri-state buffer between adjacent memory banks along the same bus comprises interposing each bi-directional tri-state buffer between different ones of the memory banks arranged in the same row or column.

9 . A method of operating a memory device, comprising:

coupling at least two of a plurality of memory banks to the same bus;

coupling logic to the memory banks via each bus;

interposing a bi-directional tri-state buffer between adjacent memory banks along the same bus so that each bus is segmented into a plurality of sections, each bus section being coupled to one or more different ones of the memory banks; and

controlling access to different ones of the memory banks during memory operations using the bi-directional tri-state buffers.

10 . The method of claim 9 , wherein controlling access to different ones of the memory banks during memory operations using the bi-directional tri-state buffers comprises:

determining which bank is to be accessed during a memory operation; and

activating each bi-directional tri-state buffer interposed between the logic and the bank to be accessed along the bus that couples the bank to the logic.

11 . The method of claim 10 , wherein activating each bi-directional tri-state buffer interposed between the logic and the bank to be accessed along the bus that couples the bank to the logic comprises activating read driver circuitry included in each bi-directional tri-state buffer interposed between the logic and the bank to be accessed during a read operation along the bus that couples the bank to the logic.

12 . The method of claim 10 , wherein activating each bi-directional tri-state buffer interposed between the logic and the bank to be accessed along the bus that couples the bank to the logic comprises activating write driver circuitry included in each bi-directional tri-state buffer interposed between the logic and the bank to be accessed during a write operation along the bus that couples the bank to the logic.

13 . The method of claim 10 , further comprising deactivating each bi-directional tri-state buffer disposed further from the logic than the bank to be accessed along the bus that couples the logic to the bank to be accessed.

14 . A memory device, comprising:

a first group of memory banks operable to share a first bus;

a second group of memory banks operable to share a second bus;

logic coupled to the groups of memory banks via the respective buses, the logic operable to control access to the memory banks; and

wherein each bus is segmented into a plurality of sections by one or more bi-directional tri-state buffers, each bi-directional tri-state buffer interposed between adjacent ones of the memory banks that share the same bus.

15 . The memory device of claim 14 , wherein the logic is operable to:

determine which bank is to be accessed during a memory operation; and

activate each bi-directional tri-state buffer interposed between the logic and the bank to be accessed along the bus that couples the bank to the logic.

16 . The memory device of claim 15 , wherein the memory operation is a read operation and the logic is operable to activate read driver circuitry included in each bi-directional tri-state buffer interposed between the logic and the bank to be accessed during the read operation along the bus that couples the bank to the logic.

17 . The memory device of claim 15 , wherein the memory operation is a write operation and the logic is operable to activate write driver circuitry included in each bi-directional tri-state buffer interposed between the logic and the bank to be accessed during the write operation along the bus that couples the bank to the logic.

18 . The memory device of claim 15 , wherein the logic is operable to deactivate each bi-directional tri-state buffer disposed further from the logic than the bank to be accessed along the bus that couples the logic to the bank to be accessed.

19 . A memory device, comprising:

a first group of memory banks operable to share a bus;

a second group of memory banks operable to share the same bus with the first group of memory banks;

logic coupled to the groups of memory banks via the bus, the logic operable to control access to the memory banks; and

wherein the bus is segmented into a plurality of sections by one or more bi-directional tri-state buffers, each bi-directional tri-state buffer interposed between adjacent ones of the memory banks along the bus.

20 . The memory device of claim 19 , wherein the logic is operable to:

determine which bank is to be accessed during a memory operation; and

activate each bi-directional tri-state buffer interposed between the logic and the bank to be accessed.

21 . The memory device of claim 20 , wherein the memory operation is a read operation and the logic is operable to activate read driver circuitry included in each bi-directional tri-state buffer interposed between the logic and the bank to be accessed during the read operation.

22 . The memory device of claim 20 , wherein the memory operation is a write operation and the logic is operable to activate write driver circuitry included in each bi-directional tri-state buffer interposed between the logic and the bank to be accessed during the write operation.

23 . The memory device of claim 20 , wherein the logic is operable to deactivate each bi-directional tri-state buffer disposed further from the logic than the bank to be accessed along the bus.

24 . A system comprising a memory device having a plurality of memory banks with at least two of the memory banks operable to share the same bus, logic coupled to the memory banks via the different buses and operable to control access to the memory banks and a bi-directional tri-state buffer interposed between adjacent memory banks along the same bus so that each bus is segmented into a plurality of sections, each bus section being coupled to one or more different ones of the memory banks.