Phase change memory fabricated using self-aligned processing
View Patent ↗A memory includes transistors in rows and columns providing an array, conductive lines in columns across the array, and phase change elements contacting the conductive lines and self-aligned to the conductive lines. The memory includes bottom electrodes contacting the phase change elements, each bottom electrode self-aligned to a conductive line and coupled to one side of a source-drain path of a transistor.
1. A memory comprising:
transistors in rows and columns providing an array;
bit lines in columns across the array;
phase change elements directly contacting the bit lines and self-aligned to the bit lines; and
bottom electrodes directly contacting the phase change elements, each bottom electrode self-aligned to a bit line and coupled to one side of a source-drain path of a transistor.
2. The memory of claim 1 , wherein each bottom electrode is self-aligned to a phase change element on a side perpendicular to the bit lines.
3. The memory of claim 1 , further comprising:
ground lines in rows across the array, each ground line coupled to the other side of the source-drain path of the transistors in each row.
4. The memory of claim 1 , further comprising:
word lines in rows across the array, each word line coupled to gates of the transistors in each row.
5. The memory of claim 1 , wherein the memory is scalable to 6F 2 , where F is the minimum feature size.
6. The memory of claim 1 , wherein the memory is scalable to 8F 2 , where F is the minimum feature size.
7. A memory comprising:
transistors in rows and columns providing an array;
bit lines in columns across the array;
phase change material in columns across the array and providing storage locations, the phase change material directly contacting the bit lines and self-aligned to the bit lines; and
bottom electrodes directly contacting the storage locations, each bottom electrode self-aligned to a bit line and coupled to one side of a source-drain path of a transistor.
8. The memory of claim 7 , wherein each bottom electrode is self-aligned to a storage location on a side perpendicular to the bit lines.
9. The memory of claim 7 , further comprising:
ground lines in rows across the array, each ground line coupled to the other side of the source-drain path of the transistors in each row.
10. The memory of claim 7 , further comprising:
word lines in rows across the array, each word line coupled to gates of the transistors in each row.
11. The memory of claim 7 , wherein the memory is scalable to 6F 2 , where F is the minimum feature size.
12. The memory of claim 7 , wherein the memory is scalable to 8F 2 , where F is the minimum feature size.
13. A memory comprising:
transistors in rows and columns providing an array;
bit lines in columns across the array;
top electrodes contacting the bit lines and self-aligned to the bit lines;
phase change elements directly contacting the top electrodes and self-aligned to the bit lines; and
bottom electrodes directly contacting the phase change elements, each bottom electrode self-aligned to a bit line and coupled to one side of a source-drain path of a transistor.
14. The memory of claim 13 , wherein each bottom electrode is self-aligned to a phase change element on a side perpendicular to the bit lines.
15. The memory of claim 13 , wherein each top electrode is self-aligned to a phase change element on a side perpendicular to the bit lines.
16. The memory of claim 13 , further comprising:
ground lines in rows across the array, each ground line coupled to the other side of the source-drain path of the transistors in each row.
17. The memory of claim 13 , further comprising:
word lines in rows across the array, each word line coupled to gates of the transistors in each row.
18. The memory of claim 13 , wherein the memory is scalable to 6F 2 , where F is the minimum feature size.
19. The memory of claim 13 , wherein the memory is scalable to 8F 2 , where F is the minimum feature size.