Method for forming an integrated memory device and memory device
View Patent ↗The invention in one of the embodiments refers to a method for forming an integrated memory device, the method including a forming a plurality of bitlines, wherein forming the plurality of bitlines includes forming diffusion lines in a substrate, forming an electrically conductive silicidation barrier layer on a substrate surface exposed, and depositing a conductive layer comprising a metal on the silicidation barrier layer.
1. An integrated memory device comprising:
a substrate comprising a substrate surface;
a plurality of bitlines extending along a first direction parallel to the substrate surface, the bitlines being covered with conductor line isolations, wherein the bitlines each include: a diffusion line arranged in the substrate, a first conductor line portion arranged over the substrate surface and comprising a silicidation barrier layer and a second conductor line portion arranged on the first conductor line portion and comprising a metal;
a plurality of wordlines extending along a second direction parallel to the substrate surface, the second direction being different from the first direction and the wordlines being arranged more distant from the substrate surface than the bitlines; and
a plurality of memory cells each comprising a charge-trapping layer sandwiched between a first dielectric layer and a second dielectric layer, each memory cell being electrically connected to two respective bitlines and to one respective wordline.
2. The memory device of claim 1 , wherein each silicidation barrier layer comprises a conductive metal nitride.
3. The memory device of claim 2 , wherein each silicidation barrier layer comprises titanium nitride.
4. The memory device of claim 1 , wherein each second conductor line portion comprises a metal layer.
5. The memory device of claim 4 , wherein each second conductor line portion comprises a metal selected from the group consisting of Al, Cu, W, Ti, Ni, and Co.
6. The memory device of claim 1 , wherein the memory cells comprise flash memory cells that are programmable individually, the memory cells being arranged in a memory array that comprises a plurality of sectors, in each sector the memory cells of the respective sector being commonly erasable in case of an erase operation performed.
7. The memory device of claim 6 , wherein the charge-trapping layer of each memory cell comprises a silicon nitride layer.
8. The memory device of claim 1 , wherein the diffusion lines comprise an n-type dopant arranged in the substrate.
9. The memory device of claim 1 , wherein each diffusion line of a bitline electrically connects two respective rows of memory cells adjacent to the respective bitline.
10. The memory device of claim 1 , further comprising spacers arranged between sidewalls of gate stacks of the memory cells and conductor line portions of the bitlines.
11. The memory device of claim 10 , wherein the spacers comprise oxide spacers.
12. The memory device of claim 1 , wherein the conductor line isolations covering the bitlines comprise an oxide.
13. The memory device of claim 1 , wherein the gate stacks of memory cells are each covered with a cap dielectric layer, the cap dielectric layer being made of a material different from the material of the conductor line isolations covering the bitlines.
14. An integrated memory device comprising:
a substrate comprising a substrate surface;
a plurality of bitlines extending along a first direction parallel to the substrate surface, the bitlines being covered with conductor line isolations, wherein the bitlines each include: a diffusion line arranged in the substrate and a conductor line portion arranged over the substrate surface and comprising a monocrystalline doped semiconductor material;
a plurality of wordlines extending along a second direction parallel to the substrate surface, the second direction being different from the first direction and the wordlines being arranged more distant from the substrate surface than the bitlines; and
a plurality of memory cells each comprising a charge-trapping layer sandwiched between a first dielectric layer and a second dielectric layer, each memory cell being electrically connected to two respective bitlines and to one respective wordline.
15. The memory device of claim 14 , wherein each conductor line portion comprises a semiconductor material epitaxially grown on the substrate surface.
16. The memory device of claim 15 , wherein the substrate comprises a silicon substrate and wherein the conductor line portions are formed of doped monocrystalline silicon.
17. The memory device of claim 14 , wherein the conductor line portions comprise a dopant concentration greater than 10 19 /cm 3 .
18. The memory device of claim 14 , wherein the memory cells comprise flash memory cells that are programmable individually, the memory cells being arranged in a memory array that comprises a plurality of sectors, in each sector the memory cells of the respective sector being commonly erasable in case of an erase operation performed.
19. The memory device of claim 18 , wherein the charge-trapping layer of each memory cell comprises a silicon nitride layer.
20. The memory device of claim 14 , wherein the diffusion lines comprise an n-type dopant arranged in the substrate.
21. The memory device of claim 14 , wherein each diffusion line of a bitline electrically connects two respective rows of memory cells adjacent to the respective bitline.
22. The memory device of claim 14 , further comprising spacers arranged between sidewalls of gate stacks of the memory cells and conductor line portions of the bitlines.
23. The memory device of claim 22 , wherein the spacers comprise oxide spacers.
24. The memory device of claim 14 , wherein the conductor line isolations covering the bitlines comprise an oxide.
25. The memory device of claim 14 , wherein the gate stacks of memory cells are each covered with a cap dielectric layer, the cap dielectric layer being made of a material different from the material of the conductor line isolations covering the bitlines.
26. An integrated memory device comprising:
a substrate comprising a substrate surface;
a plurality of bitlines extending along a first direction parallel to the substrate surface, the bitlines being covered with conductor line isolations, wherein the bitlines each include: a diffusion line arranged in the substrate and a conductor line portion arranged in contact with the diffusion line in the substrate surface and comprising a monocrystalline doped semiconductor material;
a plurality of wordlines extending along a second direction parallel to the substrate surface, the second direction being different from the first direction and the wordlines being arranged more distant from the substrate surface than the bitlines; and
a plurality of memory cells each comprising a charge-trapping layer sandwiched between a first dielectric layer and a second dielectric layer, each memory cell being electrically connected to two respective bitlines and to one respective wordline.