IP Library Granted Patent US 7,915,603
Granted Patent B2
US 7,915,603 · App. 11/588,865 · Granted Mar 29, 2011

Modifiable gate stack memory element

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Quick Facts
Patent No.
US 7,915,603
App. No.
11/588,865
Granted
Mar 29, 2011
Kind
B2
Abstract

An apparatus and method for storing information are provided, including using a transistor having a channel, a gate oxide layer, a gate electrode, and a modifiable gate stack layer. The on-resistance of the transistor is changed by causing a non-charge-storage based physical change in the modifiable gate stack layer, to store information.

Claims (15)

1. A memory cell comprising:

a transistor comprising a channel, a gate dielectric layer, a gate electrode, and a modifiable insulating layer disposed under the gate electrode and with at least a portion of the modifiable insulating layer in contact with the gate dielectric layer,

wherein information stored in the memory cell depends on a changeable conductivity of the modifiable insulating layer, wherein the modifiable insulating layer comprises a low conductivity material, and wherein forming a highly conductive filament in the low conductivity material changes a conductivity of the modifiable insulating layer.

2. The memory cell of claim 1 , wherein the low conductivity material comprises a solid electrolyte.

3. The memory cell of claim 1 , wherein the low conductivity material comprises an sp 3 -rich carbon layer, and wherein the highly conductive filament comprises an sp 2 -rich carbon filament formed in the sp 3 -rich carbon layer.

4. The memory cell of claim 1 , wherein applying a first current through the modifiable insulating layer induces formation of the highly conductive filament.

5. The memory cell of claim 4 , wherein applying a second current through the modifiable insulating layer, the second current flowing in an opposite direction with respect to the first current, reverses the formation of the highly conductive filament.

6. A semiconductor transistor comprising:

a source, a drain, and a channel between the source and the drain;

a gate dielectric layer disposed over the channel;

a gate electrode; and

a resistive switching element disposed under the gate electrode and with at least a portion of the resistive switching element in contact with the gate dielectric layer, a conductivity of the resistive switching element being changeable to alter an on-resistance of the semiconductor transistor, wherein

the resistive switching element comprises an insulating material, and wherein the conductivity of the resistive switching element is changed by reversibly forming a conductive filament in the insulating material, wherein

the conductive filament is formed adjacent the source or the drain, wherein

the conductive filament is formed adjacent the source and a second conductive filament is formed adjacent the drain.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 30, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 037171/0719 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 19, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 037147/0487 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 22, 2007
From: KREUPL, FRANZ
To: QIMONDA AG
Reel/Frame 018784/0891 →