IP Library Granted Patent US 7,733,815
Granted Patent B2
US 7,733,815 · App. 11/494,848 · Granted Jun 8, 2010

Data sampler including a first stage and a second stage

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Quick Facts
Patent No.
US 7,733,815
App. No.
11/494,848
Granted
Jun 8, 2010
Kind
B2
Abstract

A data sampler including a first stage and a second stage. The first stage is configured to receive differential signals and provide a first edge rate in a first output signal and a second edge rate in a second output signal based on the differential signals. The second stage is configured to amplify the difference between the first output signal and the second output signal to provide regenerated output signals. The second stage provides a third edge rate in a first internal signal and a fourth edge rate in a second internal signal based on the first edge rate and the second edge rate.

Claims (64)

1. A data sampler comprising:

a first stage configured to receive differential signals and provide, based on the differential signals, a signal transition having a first edge rate in a first output signal and a signal transition having a second edge rate in a second output signal, wherein the first edge rate is different than the second edge rate; and

a second stage configured to amplify the difference between the first output signal and the second output signal to provide regenerated output signals, wherein the second stage provides, based on the first edge rate and the second edge rate, a signal transition having a third edge rate in a first internal signal and a signal transition having a fourth edge rate in a second internal signal;

wherein the first output signal and the second output signal are pre-charged to a first voltage during one state of a clock signal and the first internal signal and the second internal signal are pre-charged to a second voltage in response to the pre-charged first output signal and the pre-charged second output signal.

2. The data sampler of claim 1 , wherein the first output signal and the second output signal transition to a third voltage in response to an edge of the clock signal and the first internal signal and the second internal signal transition to a fourth voltage in response to the transitions of the first output signal and the second output signal.

3. The data sampler of claim 1 , wherein the difference between the first edge rate and the second edge rate is a first pulse that has a first magnitude and the difference between the third edge rate and the fourth edge rate is a second pulse that has a second magnitude, wherein the absolute value of the second magnitude is greater than the absolute value of the first magnitude.

4. The data sampler of claim 1 , wherein the first stage is configured to evaluate the differential signals in response to a single clock signal edge.

5. The data sampler of claim 1 , wherein the differential signals are ground referenced differential signals.

6. An electronic system comprising:

a sampler configured to receive differential signals and provide regenerated output signals, wherein the sampler comprises:

a first stage configured to receive the differential signals and provide, based on the differential signals, a first output signal with a signal transition having a first edge rate and a second output signal with a signal transition having a second edge rate, wherein the first edge rate is different than the second edge rate; and

a second stage configured to receive the first output signal and the second output signal and provide a first internal signal and a second internal signal based on the first output signal and the second output signal, wherein the first output signal and the second output signal are pre-charged to a first voltage during one state of a clock signal and the first internal signal and the second internal signal are pre-charged to a second voltage based on the pre-charged first output signal and the pre-charged second output signal.

7. The electronic system of claim 6 , wherein the first stage is configured to provide transitions in the first output signal and the second output signal during an evaluation period in response to an edge of the clock signal.

8. The electronic system of claim 7 , wherein the second stage is configured to provide transitions in the first internal signal and the second internal signal during the evaluation period and in response to the transitions in the first output signal and the second output signal.

9. The electronic system of claim 6 , wherein the second stage is configured to provide the regenerated output signals based on the difference between the first internal signal and the second internal signal.

10. The electronic system of claim 6 , comprising:

a latch configured to receive the regenerated output signals and provide at least one data output signal.

11. The electronic system of claim 6 , wherein the second stage is configured to provide, based on the first edge rate and the second edge rate, a signal transition having a third edge rate in the first internal signal and a signal transition having a fourth edge rate in the second internal signal.

12. A data sampler comprising:

means for receiving differential signals at a first stage;

means for providing, based on the differential signals, a first output signal with a signal transition having a first edge rate and a second output signal with a signal transition having a second edge rate, wherein the first edge rate is different than the second edge rate;

means for pre-charging the first output signal and the second output signal to a first voltage based on a clock signal;

means for receiving the first output signal and the second output signal at a second stage;

means for providing a first internal signal and a second internal signal based on the first output signal and the second output signal; and

means for pre-charging the first internal signal and the second internal signal to a second voltage based on the pre-charged first output signal and the pre-charged second output signal.

13. The data sampler of claim 12 , comprising:

means for amplifying the difference between the first internal signal and the second internal signal to provide regenerated output signals; and

means for latching the regenerated output signals to provide at least one data output signal.

14. The data sampler of claim 12 , wherein the means for providing a first internal signal and a second internal signal comprises:

means for providing, based on the first edge rate and the second edge rate, a signal transition having a third edge rate in the first internal signal and a signal transition having a fourth edge rate in the second internal signal.

15. A data sampler comprising:

means for receiving differential signals at a first stage;

means for providing, based on the differential signals, a signal transition having a first edge rate in a first output signal and a signal transition having a second edge rate in a second output signal, wherein the first edge rate is different than the second edge rate;

means for receiving the first output signal and the second output signal at a second stage; and

means for providing, based on the first edge rate and the second edge rate, a signal transition having a third edge rate in a first internal signal and a signal transition having a fourth edge rate in a second internal signal;

wherein the means for providing a signal transition having a first edge rate in a first output signal and a signal transition having a second edge rate in a second output signal comprises:

means for pre-charging the first output signal and the second output signal to a first voltage based on a clock signal; and

means for transitioning the first output signal and the second output signal to a second voltage in response to an edge of the clock signal.

16. The data sampler of claim 15 , wherein the means for providing a signal transition having a third edge rate in a first internal signal and a signal transition having a fourth edge rate in a second internal signal comprises:

means for pre-charging the first internal signal and the second internal signal to a third voltage in response to the pre-charged first output signal and the pre-charged second output signal; and

means for transitioning the first internal signal and the second internal signal to a fourth voltage in response to the transitioned first output signal and the transitioned second output signal.

17. A method for sampling data comprising:

receiving differential signals at a first stage;

pre-charging a first output signal and a second output signal to a first voltage based on a clock signal;

pre-charging a first internal signal and a second internal signal to a second voltage based on the pre-charged first output signal and the pre-charged second output signal;

transitioning, based on the differential signals, the first output signal at a first edge rate and the second output signal at a second edge rate, wherein the first edge rate is different than the second edge rate;

receiving the first output signal and the second output signal at a second stage; and

transitioning the first internal signal and the second internal signal based on the first output signal and the second output signal.

18. The method of claim 17 , comprising:

amplifying the difference between the first internal signal and the second internal signal to provide regenerated output signals; and

latching the regenerated output signals to provide at least one data output signal.

19. The method of claim 17 , wherein transitioning the first internal signal and the second internal signal comprises:

providing a signal transition having a third edge rate in the first internal signal and a signal transition having a fourth edge rate in the second internal signal based on the first edge rate and the second edge rate.

20. A method for sampling data comprising:

receiving differential signals at a first stage;

providing, based on the differential signals, a signal transition having a first edge rate in a first output signal and a signal transition having a second edge rate in a second output signal, wherein the first edge rate is different than the second edge rate;

receiving the first output signal and the second output signal at a second stage; and

providing a signal transition having a third edge rate in a first internal signal and a signal transition having a fourth edge rate in a second internal signal based on the first edge rate and the second edge rate;

wherein providing a signal transition having a first edge rate in a first output signal and a signal transition having a second edge rate in a second output signal comprises:

pre-charging the first output signal and the second output signal to a first voltage based on a clock signal; and

transitioning the first output signal and the second output signal to a second voltage in response to an edge of the clock signal.

21. The method of claim 20 , wherein providing a signal transition having a third edge rate in a first internal signal and a signal transition having a fourth edge rate in a second internal signal comprises:

pre-charging the first internal signal and the second internal signal to a third voltage in response to the pre-charged first output signal and the pre-charged second output signal; and

transitioning the first internal signal and the second internal signal to a fourth voltage in response to the transitioned first output signal and the transitioned second output signal.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 30, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 037171/0719 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 19, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 037147/0487 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2007
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 019569/0514 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2006
From: INFINEON TECHNOLOGIES NORTH AMERICA CORP.
To: INFINEON TECHNOLOGIES AG
Reel/Frame 018298/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 14, 2006
From: GOPALAKRISHNAN, KARTHIK; RAVEZZI, LUCA; CHOKKALINGAM, SIVARAMAN; PARTOVI, HAMID
To: INFINEON TECHNOLOGIES NORTH AMERICA CORP.
Reel/Frame 018097/0269 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 14, 2006
From: PRETE, EDOARDO
To: INFINEON TECHNOLOGIES AG
Reel/Frame 018097/0280 →