Resistive memory element and method of fabrication

1. An integrated circuit, comprising:

a buried gate select transistor comprising a source region and a drain region; and

a resistive memory element coupled to the buried gate select transistor, the resistive memory element storing information based on a resistivity of the resistive memory element, the resistive memory element comprising a stack of a plurality of layers, the stack comprising a bottom contact layer, a switching layer disposed above the bottom contact layer and a top contact layer disposed above the switching layer;

a common line;

wherein the drain region of the buried gate select transistor is in direct physical contact to the bottom contact layer of the stack of the resistive memory element; and

wherein the source region of the buried gate select transistor is in direct physical contact to the common line wherein the buried gate select transistor comprises: a recess formed in an active area of a substrate, the active area comprising a source region and a drain region, the recess located between the source region and the drain region; a gate oxide layer lining the recess; and a gate comprising a conductive material at least partially filling the recess.

2. The integrated circuit of claim 1 , wherein the resistive memory element comprises a transition metal oxide material.

3. The integrated circuit of claim 2 , wherein the transition metal oxide material comprises a material selected from the group consisting of NiO, TiO2, HfO2, ZrO2, Nb2O5, and Ta2O5.

4. The integrated circuit of claim 1 , wherein the resistive memory element comprises a switching layer that switches between a high resistance state and a low resistance state by reversibly forming a conductive filament within the switching layer.

5. A method of manufacturing an integrated circuit, the method comprising:

forming a buried gate select transistor comprising a source region and a drain region; and

forming a resistive memory element coupled to the buried gate transistor, the resistive memory element storing information based on a resistivity of the resistive memory element, the resistive memory element comprising a stack of a plurality of layers, the stack comprising a bottom contact layer, a switching layer disposed above the bottom contact layer and a top contact layer disposed above the switching layer

directly contacting the drain region of the buried gate select transistor to the bottom contact layer, and

forming a common line such that it is in direct physical contact to the source region of the buried gate select transistor wherein the buried gate select transistor comprises: a recess formed in an active area of a substrate, the active area comprising a source region and a drain region, the recess located between the source region and the drain region; a gate oxide layer lining the recess; and a gate comprising a conductive material at least partially filling the recess.

6. The method of claim 5 , wherein forming the switching layer comprises depositing a transition metal oxide material.

7. The method of claim 6 , wherein depositing the transition metal oxide material comprises depositing a material selected from the group consisting of NiO, TiO2, HfO2, ZrO2, Nb2O5, and Ta2O5.

8. The method of claim 5 , further comprising forming a bit line electrically coupled to the resistive memory element.

9. An integrated circuit comprising:

a buried gate select transistor, the buried gate select transistor comprising a trench formed in a substrate, a gate oxide layer lining the trench, a gate at least partially filling the trench, a source region and a drain region; and

a resistive memory element disposed above the buried gate select transistor, the resistive memory element comprising a stack of a plurality of layers, the stack comprising a bottom contact layer, a switching layer disposed above the bottom contact layer and a top contact layer disposed above the switching layer;

a common line;

wherein the drain region of the buried gate select transistor is in direct physical contact to the bottom contact layer of the stack of the resistive memory element; and

wherein the source region of the buried gate select transistor is in direct physical contact to the common line.

10. The integrated circuit of claim 9 , wherein the resistive memory element comprises a transition metal oxide material.

11. The integrated circuit of claim 9 , wherein the resistive memory element comprises a switching layer that switches between a high resistance state and a low resistance state by reversibly forming a conductive filament within the switching layer.

12. A memory module comprising:

a plurality of integrated circuits that are electrically coupled to one another, wherein the integrated circuits each comprise a memory cell comprising a buried gate select transistor comprising a source region and a drain region and a resistive memory element coupled to the buried gate select transistor, the resistive memory element storing information based on a resistivity of the resistive memory element, the resistive memory element comprising a stack of a plurality of layers, the stack comprising a bottom contact layer, a switching layer disposed above the bottom contact layer and a top contact layer disposed above the switching layer;

a common line;

wherein the drain region of the buried gate select transistor is in direct physical contact to the bottom contact layer of the stack of the resistive memory element; and

wherein the source region of the buried gate select transistor is in direct physical contact to the common line wherein the buried gate select transistor comprises: a recess formed in an active area of a substrate, the active area comprising the source region and the drain region, the recess located between the source region and the drain region; a gate oxide layer lining the recess; and a gate comprising a conductive material at least partially filling the recess.

13. The memory module of claim 12 , wherein the restive memory element comprises a transition metal oxide material.

14. The memory module of claim 12 , wherein the resistive memory element comprises a switching layer that switches between a high resistance state and a low resistance state by reversibly forming a conductive filament within the switching layer.