Parallel read for front end compression mode

1. A method of testing a memory device in a first test mode, comprising:

reading a plurality of bits from multiple banks of the memory device in parallel;

generating, from the plurality of bits read from each bank, a reduced number of compressed test data bits;

routing the compressed test data bits from each bank to a common set of data lines shared between the multiple banks; and

providing the compressed test data bits as output on one or more data pins of the memory device, wherein generating the reduced number of compressed data bits comprises comparing sets of the plurality of data bits to one or more known test data patterns previously written to the memory banks.

2. The method of claim 1 , wherein routing the compressed test data bits from each bank to a common set of data lines shared between the multiple banks comprises:

routing a first set of compressed test data bits generated from a plurality of bits read from a first bank to a first subset of the common set of data lines; and

routing a second set of compressed test data bits generated from a plurality of bits read from a second bank to a second subset of the common set of data lines, wherein compressed test data bits generated from a plurality of bits read from the second bank are routed to the first subset of the common set of data lines when the memory device is in a second test mode.

3. The method of claim 1 , wherein generating the reduced number of compressed test data bits comprises generating a single bit based on at least four data bits read from a memory bank.

4. The method of claim 1 , wherein each bit in a set of bits compared to a known test data pattern is formed at an intersection of a column select line and a word line.

5. The method of claim 1 , wherein the first bank is selected from a first group of four or more banks and the second bank is selected from a second group of four or more banks.

6. A dynamic random access memory (DRAM) device, comprising:

at least two groups of memory cell banks, wherein a first set of common data lines is shared between banks in each group and a second set of common data lines is shared between the groups;

one or more test logic circuits, each configured to generate, from a plurality of bits read from a bank, a single pass/fail bit indicating whether the corresponding plurality of bits matches predefined test data; and

logic configured to route a plurality of bits from multiple banks of the memory device to the test logic circuits in parallel, route the compressed test data bits from each bank to the first set of common data lines shared between the groups, and provide the compressed test data bits as output on one or more data pins of the memory device.

7. The memory device of claim 6 , wherein:

the plurality of banks comprises at least two groups of memory banks, with banks in each group sharing a first common set of data lines and the groups sharing a second set of common data lines; and

the one or more test logic circuits comprise a test logic circuit for each group of memory banks.

8. The memory device of claim 7 , wherein the test logic for each group of memory banks generates a reduced number of test data bits from data received on the first common set of data lines and routes the reduced number of compressed data bits to the second set of common data lines.

9. The memory device of claim 6 , wherein the plurality of banks comprises more than four banks.

10. The memory device of claim 6 , wherein the logic is configured to provide multiple bits of the compressed test data bits as output on one or more data pins of the memory device on successive clock cycle edges.

11. A system, comprising:

a tester; and

one or more memory devices, each comprising a plurality of banks of memory cells and logic configured to, when the memory device has been placed in a test mode by the tester, read a plurality of bits from multiple banks of the memory device in parallel, generate, from the plurality of bits read from each bank, a reduced number of one or more compressed test data bits, route the compressed test data bits from each bank to a common set of data lines shared between the multiple banks, and provide the compressed test data bits as output on one or more data pins, wherein the logic is configured to generate a reduced number of one or more compressed data bits by comparing bits of data read to predefined test data in a register.

12. The system of claim 11 , wherein the multiple banks comprise a first bank selected from a first group of four or more banks and a second bank selected from a second group of four or more banks.

13. The system of claim 11 , wherein the tester is configured to place the one or more memory devices in the test mode via a mode register set (MRS) command.