Method of manufacturing a field effect transistor device with recessed channel and corner gate device
View Patent ↗Fabrication of recessed channel array transistors (RCAT) with a corner gate device includes forming pockets between a semiconductor fin that includes a gate groove and neighboring shallow trench isolations that extend along longs sides of the semiconductor fin. A protection liner covers the semiconductor fin and the trench isolations in a bottom portion of the gate groove and the pockets. An insulator collar is formed in the exposed upper sections of the gate groove and the pockets, wherein a lower edge of the insulator collar corresponds to a lower edge of source/drain regions formed within the semiconductor fin. The protection liner is removed. The bottom portion of the gate groove and the pockets are covered with a gate dielectric and a buried gate conductor layer. The protection liner avoids residuals of polycrystalline silicon between the active area in the semiconductor fin and the insulator collar.
1. A method of manufacturing an integrated circuit including a field effect transistor device, the method comprising;
(a) forming a gate groove in a semiconductor fin, the gate groove extending between opposing long sides of the semiconductor fin;
(b) recessing isotropically shallow trench isolations provided at the both long sides of the semiconductor fin to form pockets between the semiconductor fin and the shallow trench isolations, the pockets extending along the long sides of the semiconductor fin;
(c) forming a protection liner covering the semiconductor fin and the shallow trench isolations in a bottom portion of the gate groove and the pockets and leaving upper portions of the semiconductor fin exposed;
(d) providing an insulator collar on the exposed upper portions of the semiconductor fin and
(e) filling the gate groove and the pockets with a buried gate conductor layer.
2. The method of claim 1 , wherein (c) includes:
depositing a conformal protection liner;
depositing a sacrificial material;
recessing the sacrificial material, such that a residual portion of the sacrificial material forms a sacrificial fill covering the conformal protection liner in the bottom portions of the gate groove and the pockets, wherein the protection liner is exposed in upper portions of the gate groove and the pockets; and
removing exposed sections of the conformal protection liner, wherein a residual portion of the conformal protection liner forms the protection liner.
3. The method of claim 2 , wherein the conformal protection liner is deposited such that the pockets between the semiconductor fin and the shallow trench isolations are filled completely.
4. The method of claim 1 , wherein (a) includes:
depositing a mask stack on the semiconductor substrate, the mask stack covering the shallow trench isolations and the semiconductor fin;
providing an opening in the mask stack, the opening being placed symmetrically above the semiconductor fin between opposing short sides of the semiconductor fin and extending at least between the long sides of the semiconductor fin; and
etching the semiconductor fin selectively to the shallow trench isolations.
5. The method of claim 4 , wherein depositing the mask stack includes:
depositing a bottom polysilicon mask layer;
depositing an oxide mask layer; and
depositing a top polysilicon mask layer.
6. the method of claim 5 , wherein providing the opening includes:
patterning a resist layer via photolithography, the resist layer including a resist opening;
transferring the resist opening into the top polysilicon mask layer and the oxide mask layer;
forming a nitride spacer on the inner sidewall of the opening in the top polysilicon mask layer and the oxide mask layer; and
transferring the opening into the bottom polysilicon mask layer.
7. The method of claim 5 , wherein providing the opening includes:
patterning a resist layer via photolithography, the resist layer including a resist opening;
patterning the mask stack according to the pattern of the resist layer, wherein the resist opening is transferred into the mask stack; and
forming a nitride spacer on the inner sidewall of the opening of the mask stack.
8. The method of claim 1 , wherein (d) comprises a thermal oxidation of silicon to form the insulator collar.
9. The method of claim 1 , wherein (d) includes depositing a dielectric material at a bottom portion of the gate groove.
10. The method of claim 1 , wherein a first and a second source/drain region are provided within the semiconductor fin, the first source/drain region being formed within a first section of the semiconductor fin adjoining a first short side, the second source/drain region being formed within a second section of the semiconductor fin adjoining a second short side opposing the first short side, wherein the first and second source/drain regions are formed in upper portions of the semiconductor fin adjacent to the insulator collar.
11. The method of claim 1 , further comprising removing the protection liner, after (d) and before (e).
12. The method of claim 11 , further comprising providing a gate dielectric covering the semiconductor fin in the bottom portion of the gate groove and the pockets after removing the protection liner.
13. The method of claim 1 , wherein the recess starts from interface planes of the gate groove and the shallow trench isolations.