Memory including a write training block

1. A memory, comprising:

a plurality of first-in-first-out (FIFO) cells;

an output pointer counter for switching a value of a FIFO output pointer among the FIFO cells; and

a write training block for generating information for moving the FIFO output pointer based on data read from the FIFO cells.

2. The memory of claim 1 , further comprising:

an input pointer counter for switching a value of a FIFO input pointer among the FIFO cells.

3. The memory of claim 1 , wherein the write training block receives the value of the FIFO output pointer and data read-out from the FIFO cells.

4. The memory of claim 1 , wherein the write training block switches the memory between a normal mode with a normal write cycle and a write training mode with an extended write cycle.

5. The memory of claim 1 , wherein a TDQSS of the memory has a range greater than one-half clock cycle early or late.

6. A memory, comprising:

a plurality of first-in-first-out (FIFO) cells for accepting a data pattern;

an output pointer counter for switching a value of a FIFO output pointer among the FIFO cells in response to an external clock; and

a write training block for extending a write cycle for reading out all the FIFO cells, for determining whether the data pattern is located in a correct position in the FIFO cells, and for generating information for moving the FIFO output pointer from one FIFO cell to another FIFO cell if it is determined that the data pattern is located in the incorrect position.

7. The memory of claim 6 , further comprising:

an input pointer counter for switching a value of a FIFO input pointer among the FIFO cells in response to a write data strobe clock signal.

8. The memory of claim 6 , wherein the write training block accepts as input the value of the FIFO output pointer and data read-out from the FIFO cells.

9. The memory of claim 6 , wherein the write training block switches the memory between a normal mode with a normal write cycle and a write training mode with the extended write cycle.

10. The memory of claim 6 , wherein a TDQSS of the memory has a range greater than one-half clock cycle early or late.

11. A method of synchronizing a write data strobe clock signal with an external clock signal, comprising:

writing a data pattern into a first-in-first-out (FIFO) buffer;

determining whether the data pattern is in a correct location in the FIFO buffer with respect to an external clock; and

moving a FIFO output pointer if the data pattern is determined to be in an incorrect location in the FIFO buffer.

12. The method of claim 11 , further comprising:

executing a plurality of no-operation (NOP) operations for resetting the FIFO buffer.

13. The method of claim 11 , wherein writing the data pattern comprises:

writing a data pattern comprising a plurality of ones and only a single zero.

14. The method of claim 11 , further comprising:

receiving a start command from an extended memory register set (EMRS).

15. The method of claim 11 , further comprising:

reading out the entire content of the FIFO buffer.

16. A method of synchronizing a write data strobe clock signal with an external clock signal, comprising:

(a) writing a data pattern into a first-in-first out (FIFO) buffer;

(b) determining whether the data pattern is in a correct location in the FIFO with respect to an external clock;

(c) moving a FIFO output pointer if the data pattern is determined to be in an incorrect location in the FIFO; and

repeating (a), (b) and (c) until the data pattern is determined to be in the correction location.

17. The method of claim 16 , wherein writing the data pattern comprises:

writing a data pattern comprising a plurality of ones and only a single zero.

18. The method of claim 16 , further comprising:

receiving a start command from an extended memory register set (EMRS).

19. The method of claim 16 , further comprising:

reading out the entire content of the FIFO buffer.

20. A random access memory, comprising:

means for writing a data pattern into a first-in-first-out (FIFO) buffer;

means for determining whether the data pattern is in a correct location in the FIFO buffer with respect to an external clock; and

means for moving a FIFO output pointer if the data pattern is determined to be in an incorrect location in the FIFO buffer.

21. The random access memory of claim 20 , further comprising:

means for executing a plurality of no-operation (NOP) operations for resetting the FIFO buffer.

22. The random access memory of claim 20 , wherein means for writing the data pattern comprises:

means for writing a data pattern comprising a plurality of ones and only a single zero.

23. The method of claim 20 , further comprising:

means for receiving a start command from an extended memory register set (EMRS).

24. The method of claim 20 , further comprising:

means for reading out the entire content of the FIFO buffer.