Manufacturing method for an integrated semiconductor structure

1. A manufacturing method for an integrated semiconductor structure comprising the steps of:

providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device region;

forming caps made of one or more layers of a cap material over said plurality of gate stacks in said memory cell region and over said at least one gate stack in said peripheral device region;

forming a first contact hole between two neighboring gate stacks in said memory cell region;

depositing a first protective layer over said memory cell region and peripheral device region;

exposing said cap of said at least one gate stack in said peripheral device region;

modifying said exposed cap of said at least one gate stack in said peripheral device region in a process step wherein said first protective layer acts as a mask in said memory cell region;

forming a second protective layer over said modified cap in said peripheral device region;

partly removing said first and second protective layer in order to bring said first and second protective layer to about a same upper level;

removing said first protective layer from said first contact hole;

forming at least one another contact hole in said peripheral device region, said at least one another contact hole exposing another contact area which is located either adjacent to said gate stack or in said gate stack in said peripheral device region; and

filling said contact hole and said at least one another contact hole with a respective contact plug.

2. The method according to claim 1 , wherein a third protective layer is formed between said caps of said plurality of gate stacks in said memory cell region and over said cap of said at least one gate stack in said peripheral device region; wherein a first spacer is structured from said third protective layer adjacent to said cap of said at least one gate stack in said peripheral device region; and wherein an etch step using said first spacer as a mask is performed to define the lateral dimensions of said another contact area which is located adjacent to said gate stack in said peripheral device region.

3. The method according to claim 1 or 2 , wherein said another contact area which is located adjacent to said gate stack in said peripheral device region is formed by exposing a part of a corresponding first active area and thereafter performing a silicidation process step in said exposed part.

4. The method according to claim 1 , wherein modifying said exposed cap of said at least one gate stack in said peripheral device region comprises the steps of at least partly removing said exposed cap from said at least one gate stack in said peripheral device region and depositing and structuring an additional cap material layer over said at least one gate stack in said peripheral device region in order to form a modified cap.

5. The method according to claim 1 , wherein said additional cap material layer is deposited and structured such that it forms a stress liner over said at least one gate stack in said peripheral device region.

6. The method according to claim 5 , wherein said stress liner comprises an n-FET transistor tensil stress liner and wherein said additional cap material layer subjected to the following steps: forming a thin oxide as a hard mask, exposing p-FET transistors, wet etching said oxide in a lithography step; and wet thinning or removal of said additional cap material layer over said p-FETs leaving said additional cap material layer over said n-FET transistors.

7. The method according to claim 6 , wherein said stress liner comprises an p-FET compressive stress liner and wherein the following steps are performed: forming a compressive stress liner over said p-FET transistors, forming a thin oxide as a hard mask exposing n-FET transistors, wet etching said oxide in a lithography step; and wet thinning or removal said compressive stress liner over said n-FET transistors

leaving said compressive stress liner over said p-FET transistors.

8. The method according to claim 1 , wherein said cap comprises a first, second and third nitride layer.

9. The method according to claim 1 , wherein said first, second and third protective layers are silicon oxide layers.

10. The method according to claim 4 , wherein the thickness of said additional cap material layer is chosen such that

said at least one another contact hole exposing another contact area which is located adjacent to said gate stack in said peripheral device region can be formed self-aligned to said silicided contact areas.

11. The method according to claim 1 , wherein a third protective layer is formed between said caps of said plurality of gate stacks in said memory cell region and over said cap of said at least one gate stack in said peripheral device region; wherein a first spacer is structured from said third protective layer adjacent to said cap of said at least one gate stack in said peripheral device region (PB); wherein an ion implantation step is performed into said other contact area which is located adjacent to said gate stack in said peripheral device region and uses the first spacer to define the minimum separation of the implants to the actual channel of the device.

12. The method according to claim 11 , wherein after said ion implantation step the remaining first protective layer is removed; and wherein a fourth protective layer is formed between said caps of said plurality of gate stacks in said memory cell region and over said cap of said at least one gate stack in said peripheral device region; wherein a second spacer is structured from said fourth protective layer adjacent to said cap of said at least one gate stack in said peripheral device region; and wherein an etch step using said second spacer as a mask is performed to define the lateral dimensions of said other contact area which is located adjacent to said gate stack in said peripheral device region.

13. The method according to claim 11 , wherein said fourth protective layer is made of carbon.

14. A manufacturing method for an integrated semiconductor structure comprising the steps of:

providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device region;

forming caps made of three layers of a cap material over said plurality of gate stacks in said memory cell region and over said at least one gate stack in said peripheral device region;

depositing a first protective layer over said memory cell region and peripheral device region;

exposing said cap of said at least one gate stack in said peripheral device region;

at least partly removing said exposed cap from said at least one gate stack in said peripheral device region and depositing and structuring an additional cap material layer over said at least one gate stack in said peripheral device region in order to form a modified cap, wherein said first protective layer acts as a mask in said memory cell region;

forming a second protective layer over said modified cap in said peripheral device region;

partly removing said first and second protective layer in order to bring said first and second protective layer to about a same upper level.

15. The method according to claim 14 , wherein said additional cap material layer is deposited and structured such that is forms a stress liner over said at least one gate stack in said peripheral device region.

16. The method according to claim 14 , wherein said cap comprises a first, second and third nitride layer.

17. A manufacturing method for an integrated semiconductor structure comprising the steps of:

providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device region;

forming caps made of one or more layers of a cap material over said plurality of gate stacks in said memory cell region and over said at least one gate stack in said peripheral device region;

forming a first contact hole between two neighboring gate stacks in said memory cell region;

exposing said cap of said at least one gate stack in said peripheral device region;

modifying said exposed cap of said at least one gate stack in said peripheral device region by removing said exposed cap from said at least one gate stack in said peripheral device region and depositing and structuring an additional cap material layer over said at least one gate stack in said peripheral device region in order to form a modified cap wherein said additional cap material layer is deposited and structured such that is forms a stress liner over said at least one gate stack in said peripheral device region;

forming at least one another contact hole in said peripheral device region, said at least one another contact hole exposing another contact area which is located either adjacent to said gate stack or in said gate stack in said peripheral device region; and

filling said contact hole and said at least one another contact hole with a respective contact plug.

18. The method according to claim 17 , wherein said cap comprises a first, second and third nitride layer and wherein said additional cap material layer is a fourth nitride layer.

19. The method according to claim 17 or 18 , wherein said other contact area which is located adjacent to said gate stack in said peripheral device region is formed by exposing a part of a corresponding first active area and thereafter performing a silicidation process step in said exposed part.

20. The method according to claim 17 , wherein the thickness of said additional cap material layer is chosen such that said at least one another contact hole exposing another contact area which is located adjacent to said gate stack in said peripheral device region can be formed in self-aligned manner.

21. The method according to claim 17 , wherein a protective layer is formed between said caps of said plurality of gate stacks in said memory cell region and over said cap of said at least one gate stack in said peripheral device region; wherein a first spacer is structured from said protective layer adjacent to said cap of said at least one gate stack in said peripheral device region; wherein an ion implantation step using said first spacer as a mask is performed into said another contact area which is located adjacent to said gate stack in said peripheral device region.

22. The method according to claim 21 , wherein after said ion implantation step the remaining protective layer is removed; and wherein another protective layer is formed between said caps of said plurality of gate stacks in said memory cell region and over said cap of said at least one gate stack in said peripheral device region; wherein a second spacer is structured from said another protective layer adjacent to said cap of said at least one gate stack in said peripheral device region; and wherein an etch step using said second spacer as a mask is performed to define the lateral dimensions of said another contact area which is located adjacent to said gate stack in said peripheral device region.