Memory-module controller, memory controller and corresponding memory arrangement, and also method for error correction
View Patent ↗A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of information is read either from the first memory module by means of the first address or from the second memory module by means of a second address differing from the first address. Subsequently a check is made as to whether the item of information is defective. If this is the case, the item of information is read from the respective other memory module.
1. A method for performing error correction for a memory arrangement, wherein the memory arrangement comprises a first memory module and a second memory module, the method comprising:
writing an item of information to the first memory module under a first address assigned to the first memory module;
writing the item of information to the second memory module using the first address;
reading the item of information from one of the first memory module by means of the first address and from the second memory module by means of a second address differing from the first address; and
checking whether the item of information is defective; and when the item of information is defective, the item of information is read from the other memory module, the first address being used when the other memory module is the first memory module, and the second address being used when the other memory module is the second memory module.
2. The method according to claim 1 , wherein a check is made as to whether the item of information is defective by generating at least one correction bit by means of an error correcting correction (ECC) code when writing the item of information, said correction bit forming a subset of the item of information, and wherein the at least one correction bit together with remaining bits of the item of information are evaluated in the course of reading the item of information.
3. The method according to claim 1 , wherein one or more of the first memory module and the second memory module includes a DIMM.
4. The method according to claim 1 , wherein one or more of the first memory module and the second memory module includes a fully buffered DIMM.
5. The method according to claim 1 , wherein the first memory module and the second memory module are identical with regard to speed, memory capacity and memory organization.
6. The method according to claim 1 , wherein when reading the item of information, reading is effected alternately from the first memory module and from the second memory module.
7. A memory controller for a memory arrangement comprising a first memory module and a second memory module, wherein:
the memory controller is configured to write an item of information to the first memory module under a first address assigned to the first memory module;
the memory controller is configured to read the item of information either from the first memory module by means of the first address or from the second memory module by means of a second address differing from the first address;
the memory controller is configured to check whether the item of information is defective; and
when the memory controller detects that the item of information is defective, the memory controller is configured to read the item of information from the other memory module using the first address when the other memory module is the first memory module and using the second address when the other memory module is the second memory module.
8. The memory controller according to claim 7 , wherein the memory controller is configured to generate at least one correction bit by means of an error correcting and correction (ECC) code in the course of writing the item of information, said correction bit forming a subset of the item of information, and in the course of reading the item of information the memory controller checks whether the item of information is defective by evaluating the at least one correction bit together with the remaining bits of the item of information.
9. The memory controller according to claim 7 , wherein the memory controller is configured for controlling dual in-line memory modules (DIMMs).
10. The memory controller according to claim 7 , wherein the memory controller is configured for controlling fully buffered DIMMs.
11. The memory controller according to claim 7 , wherein the memory controller is configured to be directed via its basic input-output system (BIOS) such that, upon the memory controller detecting that the item of information is defective, the memory controller does not read the item of information from the other respective memory module.