Semiconductor memory component with body region of memory cell having a depression and a graded dopant concentration
View Patent ↗A semiconductor memory component comprises at least one memory cell. The memory cell comprises a semiconductor body comprised of a body region, a drain region and a source region, a gate dielectric, and a gate electrode. The body region comprises a first conductivity type and a depression between the source and drain regions, and the source and drain regions comprise a second conductivity type. The gate electrode is arranged at least partly in the depression and is insulated from the body, source, and drain regions by the gate dielectric. The body region further comprises a first continuous region with a first dopant concentration and a second continuous region with a second dopant concentration greater than the first dopant concentration. The first continuous region adjoins the drain region, the depression and the source region, and the second region is arranged below the first region and adjoins the first region.
1. A semiconductor memory component comprising at least one memory cell; said memory cell comprising:
a semiconductor body comprised of a body region, a drain region and a source region; said body region comprising a first conductivity type and a depression between said source and drain regions, and said source and drain regions comprising a second conductivity type; body regions of adjacent memory cells are insulated from one another by an isolation trench configured to isolate the respective body regions of the adjacent memory cells along a bit line;
a gate dielectric; and
a gate electrode arranged at least partly in said depression and being insulated from said body, source, and drain regions by said gate dielectric;
said body region further comprising a first continuous region with a first dopant concentration and a second continuous region with a second dopant concentration greater than said first dopant concentration; said first continuous region adjoining said drain region, said depression and said source region, and said second region being arranged below said first region and adjoining said first region.
2. The semiconductor memory component of claim 1 , comprising a semiconductor substrate with a region of said second conductivity type on which said body region is arranged; wherein said body region comprises a further region adjoining said region of the second conductivity type and having a dopant concentration lower than said second dopant concentration.
3. The semiconductor memory component of claim 1 , comprising a dielectric layer, arranged between said body region and a semiconductor substrate.
4. The semiconductor memory component of claim 3 , wherein said body region comprises a further region adjoining said dielectric layer and having a dopant concentration greater than said second dopant concentration.
5. The semiconductor memory component of claim 4 , wherein said dopant concentration of said further region increases in the lateral direction proceeding from a central region.
6. The semiconductor memory component of claim 1 , wherein said second dopant concentration increases in the lateral direction proceeding from a central region of said second continuous region.
7. The semiconductor memory component of claim 1 , wherein the isolation trench is at least partially filled with a dielectric material.
8. The semiconductor memory component of claim 7 , comprising contact-making regions extending onto said isolation trench; said contact-making region being at least applied on said drain regions or on said source regions.
9. The semiconductor memory component of claim 1 , wherein said isolation trench is at least partially filled with a conductive material, a dielectric layer being disposed between the body region and the conductive material.
10. The semiconductor memory component of claim 9 , comprising contact-making regions extending onto said isolation trench; said contact-making region being at least applied on said drain regions or on said source regions.
11. The semiconductor memory component of claim 1 , wherein said gate dielectric is thicker in a region close to said drain or said source region than in a region in between said source and drain regions.
12. The semiconductor device of claim 1 , further comprising:
a plurality of memory cells; and
a plurality or word lines, bit lines and source lines,
wherein for each of the memory cells, the gate electrode is connected to one of the word lines, the drain region is connected to one of the bit lines, and the source region is connected to one of the source lines.
13. The semiconductor memory component of claim 1 , wherein the gate dielectric layer comprises a single layer of gate dielectric material.
14. The semiconductor memory component of claim 12 , wherein the individual word line is parallel to the source line and perpendicular to the individual bit line.
15. The semiconductor memory component of claim 12 , wherein the individual word lines and the source line are running into the same direction.