Patent Assignment
Reel/Frame 036701/0926
Assignment of Assignor's Interest
Recorded: 2015-09-28
Pages: 13
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2015-07-08
Assignee
POLARIS INNOVATIONS LIMITED
29 EARLSFORT TERRACE, DUBLIN 2, DUBLIN, IRELAND
Covered Properties
(207)
Method of Manufacturing a Dielectric Layer and Corresponding Semiconductor Device
Method for Operating a Flash Memory Device
Integrated Device and Electronic System
Electronic Device with a Memory Cell
Partially Recessed Dram Cell Structure and Method of Making the Same
Manufacturing Method for a Recessed Channel Array Transistor and Corresponding Recessed Channel Array Transistor
Redundancy Circuits for Semiconductor Memory
Closing Disk for Immersion Head
Manufacturing Method for a Trench Capacitor Having an Isolation Collar Electrically Connected with a Substrate on a Single Side via a Buried Contact for Use in a Semiconductor Memory Cell
Voltage Monitoring Test Mode and Test Adapter
Self-Refresh Circuit with Optimized Power Consumption
Sense Amplifier for Eliminating Leakage Current Due to Bit Line Shorts
Memory Having Power-Up Circuit
Distribution of Signals Throughout a Spine of an Integrated Circuit
Memory Cell Array and Method of Manufacturing the Same
Targets for Measurements in Semiconductor Devices
Patent:
7,427,774 →
Application:
11/119,029 →
Method for Reducing Lithography Pattern Defects
Patent:
7,470,503 →
Application:
11/119,320 →
Apparatus and Method for Reducing Power Consumption Within an Oscillator
Method of Manufacturing a Semiconductor Device Comprising Stacked Chips and a Corresponding Semiconductor Device
Non-Volatile Semiconductor Memory and Method for Writing Data into a Non-Volatile Semiconductor Memory
Method for Exposing a Semiconductor Wafer by Applying Periodic Movement to a Component
Lithography Method and System with Correction of Overlay Offset Errors Caused by Wafer Processing
Ecc Flag for Testing on-Chip Error Correction Circuit
Low Power Phase Change Memory Cell with Large Read Signal
Semiconductor Memory Device and Method of Production
Method and Apparatus for Adapting Circuit Components of a Memory Module to Changing Operating Conditions
Integrated Circuit Chip Having a First Delay Circuit Trimmed via a Second Delay Circuit
Test Mode for Programming Rate and Precharge Time for Dram Activate-Precharge Cycle
Method of Manufacturing a Semiconductor Device
Semiconductor Memory Device
Method of Forming a Memory Cell Array and a Memory Cell Array
Method of Programming of a Non-Volatile Memory Cell Comprising Steps of Applying Constant Voltage and Then Constant Current
Implementation of a Fusing Scheme to Allow Internal Voltage Trimming
Sensing Current Recycling Method During Self-Refresh
Reference Scheme for a Non-Volatile Semiconductor Memory Device
Sensing Scheme for a Non-Volatile Semiconductor Memory Cell
Method and Apparatus for Automated Beam Optimization in a Scanning Electron Microscope
Memory Device with Error Correction Code Module
High-Speed Interface Circuit for Semiconductor Memory Chips and Memory System Including Semiconductor Memory Chips
Memory Cell Array and Method of Forming the Same
Memory Having Parity Generation Circuit
Memory Having Parity Error Correction
Random Access Memory Having Voltage Provided Out of Boosted Supply Voltage
Multi-Chip Device and Method for Producing a Multi-Chip Device
Method of Forming a Contact in a Flash Memory Device
Output Circuit That Turns Off One of a First Circuit and a Second Circuit
Memory Device and Method for Operating the Memory Device
Multi-Chip Device and Method for Producing a Multi-Chip Device
Method for Producing Charge-Trapping Memory Cell Arrays
Handling Unit for Electronic Devices
Fluids for Immersion Lithography Systems
Synchronous Signal Generator
Method for Forming a Semiconductor Product and Semiconductor Product
Method and Apparatus for Sensing a State of a Memory Cell
Method for Programming Multi-Bit Charge-Trapping Memory Cell Arrays
Method and Apparatus for Selectively Accessing and Configuring Individual Chips of a Semi-Conductor Wafer
Non-Volatile Memory Cell Device, Programming Element and Method for Programming Data into a Plurality of Non-Volatile Memory Cells
Column Redundancy Reuse in Memory Devices
Non-Volatile Semiconductor Memory
Resistivity Changing Memory Cell Having Nanowire Electrode
Semiconductor Memory Device Including a Signal Control Device and Method of Operating the Same
Integrated Receiver Circuit
Manufacturing Method for an Integrated Semiconductor Structure and Corresponding Integrated Semiconductor Structure
Low Resistance Contact in a Semiconductor Device
Temperature Update Masking to Ensure Correct Measurement of Temperature When References Become Unstable
Clocked Standby Mode with Maximum Clock Frequency
Disabling Clocked Standby Mode Based on Device Temperature
Non-Volatile Memory Cells and Methods for Fabricating Non-Volatile Memory Cells
Substrate Based Ic-Package
Non-Volatile, Resistive Memory Cell Based on Metal Oxide Nanoparticles, Process for Manufacturing the Same and Memory Cell Arrangement of the Same
Re-Driving Cawd and Rd Signal Lines
Semiconductor Package Based on Lead-on-Chip Architecture, the Fabrication Thereof and a Leadframe for Implementing in a Semiconductor Package
Semiconductor Memory with Charge-Trapping Stack Arrangement
Semiconductor Memory Chip and Memory System
Maintaining Internal Voltages of an Integrated Circuit in Response to a Clocked Standby Mode
Method of Producing Pitch Fractionizations in Semiconductor Technology
Method of Operating a Memory Device, Memory Module, and a Memory Device Comprising the Memory Module
Technique to Suppress Leakage Current
Card Stiffener and Insertion Tool
Memory System and Method of Operating Memory System
System Memory Device Having a Dual Port
Method for Optimizing a Photolithographic Mask
Non-Volatile Semiconductor Memory and Method for Reading a Memory Cell
Memory Device and Method of Manufacturing a Memory Device
Stackable Single Package and Stacked Multi-Chip Assembly
Method and Apparatus for Monitoring Precision of Wafer Placement Alignment
Signal Routing on Redistribution Layer
Integrated Circuit Having a Switch.
Differential Duty Cycle Restoration
Delay Locked Loop Using a Fifo Circuit to Synchronize Between Blender and Coarse Delay Control Signals
Duty Cycle Corrector
Clock Controller with Integrated Dll and Dcc
Method for Processing a Layered Stack in the Production of a Semiconductor Device
Data Memory System and Method for Transferring Data into a Data Memory
Duty Cycle Detector with First and Second Oscillating Signals
Method of Forming Contacts Using Auxiliary Structures
Method for Writing Data into a Memory Cell of a Conductive Bridging Random Access Memory, Memory Circuit and Cbram Memory Circuit
Integrated Circuit Device and Method of Manufacture
Method of Manufacturing a Transistor and a Method of Forming a Memory Device with Isolation Trenches
Method for Compensating Film Height Modulations in Spin Coating of a Resist Film Layer
Semiconductor Memory Array with Serial Control/Address Bus
Semiconductor Memory Arrangement with Branched Control and Address Bus
High-Speed Interface Circuit for Semiconductor Memory Chips and Memory System Including the Same
Test Mode Method and Apparatus for Internal Memory Timing Signals
Serial Presence Detect Functionality on Memory Component
Method and Device for Generating an Output Signal Having a Predetermined Phase Shift with Respect to an Input Signal
Semiconductor Memory Device and Method for Writing Data into the Semiconductor Memory Device
Delay Locked Loop Structure Providing First and Second Locked Clock Signals
Microelectronic Device with a Plurality of Storage Elements in Serial Connection and Method of Producing the Same
Random Access Memory Including First and Second Voltage Sources
Memory Device Having an Array of Resistive Memory Cells
Phase Locked Loop Having Reduced Inherent Noise
Optical Determination of Resistivity of Phase Change Materials
Memory Device Having Low Vpp Current Consumption
Semiconductor Memory and Method for Operating a Semiconductor Memory Comprising a Plurality of Memory Cells
Redundant Wordline Deactivation Scheme
Low Equalized Sense-Amp for Twin Cell Drams
Apparatus and Method for Dynamically Controlling Data Transfer in Memory Device
Memory Device and Method for Operating a Memory Device
Semiconductor Memory Device and Method of Production
Semiconductor Memory Device and Method of Production
Semiconductor Memory Chip
Semiconductor Memory Chip
Memory Having Directed Auto-Refresh
Directed Auto-Refresh for a Dynamic Random Access Memory
Method for Forming an Isolating Trench with a Dielectric Material
Clock Circuit for Semiconductor Memories
Repair of Semiconductor Memory Device via External Command
Memory Having Parity Error Correction
Method of Transferring Signals Between a Memory Device and a Memory Controller
Integrated Circuit Having an Insulated Memory
Post Exposure Resist Bake
Generating a Sampling Clock Signal in a Communication Block of a Memory Device
Phase Change Memory Cell Including Multiple Phase Change Material Portions
Memory Device with a Plurality of Memory Cells, in Particular Pcm Memory Cells, and Method for Operating Such a Memory Cell Device
Method and Apparatus for Reducing Standby Current in a Dynamic Random Access Memory During Self Refresh
Duty Cycle Corrector
Method of Modeling Physical Layout of an Electronic Component in Channel Simulation
Memory Device That Provides Test Results to Multiple Output Pads
Apparatus for Processing a Substrate
Non-Volatile Semiconductor Memory Device and Method for Operating a Non-Volatile Memory Device
Semiconductor Memory Device Having a Redundancy Information Memory Directly Connected to a Redundancy Control Circuit
Embedded Testing Circuit for Testing a Dual Port Memory
Transistor, Memory Cell, Memory Cell Array and Method of Forming a Memory Cell Array
Methods for Elimination or Reduction of Oxide and/or Soot Deposition in Carbon Containing Layers
Circuit Board Arrangement Including Heat Dissipater
Memory Cell Arrays and Methods for Producing Memory Cell Arrays
Random Access Memory Including Circuit to Compress Comparison Results
Method for Fabricating an Integrated Circuit on a Semiconductor Substrate
Method of Fabricating an Integrated Circuit
Stack of Semiconductor Chips
Circuit Board for Reducing Crosstalk of Signals
Electrical Idle Detection Circuit Including Input Signal Rectifier
Semiconductor Memory Module with Bus Architecture
Intergrated Circuit Having Resistive Memory Cells
Controllable Delay Device
Method for Patterning a Semiconductor Component
Semiconductor Having Structure with Openings
Method for Fabricating a Nonvolatile Memory Element and a Nonvolatile Memory Element
Method and System for the Optical Inspection of Contact Faces at Semiconductor Devices with Different Appearances
Method for Fabricating an Electrical Component
Method for Fabricating a Semiconductor Component and Semiconductor Component
Multi-Context Memory Cell
Memory Element, Memory Read-Out Element and Memory Cell
Delay Locked Loop and Method for Setting a Delay Chain
Memory Module with an Electronic Printed Circuit Board and a Plurality of Semiconductor Chips of the Same Type
Semiconductor Memory Component
Contact Structure for a Stack Dram Storage Capacitor
Electronic Memory Apparatus and Method for Operating an Electronic Memory Apparatus
Memory Chip with Settable Termination Resistance Circuit
Phase Shifter
Voltage Generator Circuit, Method for Providing an Output Voltage and Electronic Memory Device
Device and Method for Regulating the Threshold Voltage of a Transistor
Dram Memory with Autoprecharge
Memory Array Architecture and Method for High-Speed Distribution Measurements
Semiconductor Memory Module with Error Correction
Method for Fabricating a Memory Cell Arrangement with a Folded Bit Line Arrangement and Corresponding Memory Cell Arrangement with a Folded Bit Line Arrangement
Device and Method for the Synchronization of Clock Signals and Adjustment of the Duty Cycle of the Clock Signal
Method for Searching for Potential Faults in a Layout of an Integrated Circuit
Semiconductor Memory System and Semiconductor Memory Chip
Stacked Capacitor and Method for Producing Stacked Capacitors for Dynamic Memory Cells
Information Transfer in Electronic Modules
Method for Producing a Trench Transistor and Trench Transistor
Integrated Semiconductor Memory with Transmission of Data via a Data Interface
Device with Memory and Method of Operating Device
Memory and Method for Improving the Reliability of a Memory Having a Used Memory Region and an Unused Memory Region
Measuring Circuit and Reading Method for Memory Cells
Circuit Arrangement and Method for Reducing Electromagnetic Interference
Dram Semiconductor Memory Device with Increased Reading Accuracy
Apparatus and Method for Avoiding Steady-State Oscillations in the Generation of Clock Signals
Memory Module Comprising a Plurality of Memory Devices
Integrated Circuit and Method of Operating Such a Circuit
Circuit Arrangement for Generating an N-Bit Output Pointer, Semiconductor Memory and Method for Adjusting a Read Latency
Synchronization Circuit for a Write Operation on a Semiconductor Memory
Memory Device Architecture and Method for Improved Bitline Pre-Charge and Wordline Timing
Semiconductor Memory Circuit, Circuit Arrangement and Method for Reading Out Data
Chip Carrier with Reduced Interference Signal Sensitivity
Storage Capacitor, a Memory Device and a Method of Manufacturing the Same
Integrated Semiconductor Memory with Determination of a Chip Temperature
Circuit Arrangement and Method for Converting Logic Signal Levels and Use of the Circuit Arrangement
Synchronization of a Digital Circuit
Semiconductor Memory Chip
Integrated Circuit Having a Fin Structure
Method of Operating an Integrated Circuit Having at Least One Memory Cell
Implementation of a Fusing Scheme to Allow Internal Voltage Trimming
Temperature Update Masking to Ensure Correct Measurement of Temperature When References Become Unstable
Signal Routing on Redistribution Layer
Related Assignments
(1)
Other recorded transfers of the patents in this record — the chain of ownership.