Low equalized sense-amp for twin cell DRAMs

1. A method of accessing a twin cell memory device, wherein the memory device comprises a twin memory cell, wherein the twin memory cell stores a data value and a complement of the data value, and wherein the data value and the complement of the data value may be accessed via a first bitline and a second bitline of the memory device, respectively, the method comprising:

precharging the first bitline and the second bitline to a low voltage, wherein the low voltage is a voltage lower than a ground voltage of the memory device;

asserting a wordline voltage to access the twin memory cell; and

sensing a voltage difference between the first and second bitline of the memory device, the voltage difference created by the data value and the complement of the data value.

2. The method of claim 1 , wherein the low voltage is a wordline off voltage.

3. The method of claim 1 , wherein the low voltage is a back bias voltage.

4. The method of claim 1 , wherein the low voltage is applied by a precharge voltage generator of the memory device, the precharge voltage generator being configured to select the low voltage from any voltage less than a ground voltage and not less than a wordline off voltage of the memory device.

5. The twin cell memory device of claim 1 , wherein the low voltage is a back bias voltage applied to a substrate of the twin cell memory device.

6. A twin cell memory device comprising:

a first bitline and a second bitline;

a twin memory cell, wherein the twin memory cell stores a data value and a complement of the data value, and wherein the data value and the complement of the data value may be accessed via the first bitline and the second bitline,

circuitry configured to:

precharge the first bitline and the second bitline to a low voltage, wherein the low voltage is a voltage lower than a ground voltage of the memory device;

assert a wordline voltage to access the twin memory cell; and

sense a voltage difference between the first and second bitline of the memory device, the voltage difference created by the data value and the complement of the data value.

7. The twin cell memory device of claim 6 , wherein the low voltage is a wordline off voltage.

8. The twin cell memory device of claim 6 , wherein the low voltage is a back bias voltage.

9. The twin cell memory device of claim 6 , further comprising:

a precharge voltage generator configured to apply the low voltage, the precharge voltage generator being configured to select the low voltage from any voltage less than a ground voltage and not less than a wordline off voltage of the memory device.

10. A twin cell memory device comprising:

a first bitline and a second bitline;

means for storing, wherein the means for storing stores a data value and a complement of the data value, and wherein the data value and the complement of the data value may be accessed via the first bitline and the second bitline,

means for controlling configured to:

precharge the first bitline and the second bitline to a low voltage, wherein the low voltage is a voltage lower than a ground voltage of the memory device;

assert a wordline voltage to access the means for storing; and

sense a voltage difference between the first and second bitline of the memory device, the voltage difference created by the data value and the complement of the data value.

11. The twin cell memory device of claim 10 , wherein the low voltage is a wordline off voltage used to deactivate a wordline of the twin cell memory device.

12. The twin cell memory device of claim 10 , further comprising:

precharge voltage generating means for selecting and applying the low voltage, wherein the low voltage is selected from between at least two voltages of a group, the group comprising:

the ground voltage, a wordline off voltage used to deactivate a wordline of the twin cell memory device, and a back bias voltage applied to a substrate of the twin cell memory device.

13. A memory device comprising:

a plurality of twin memory cells, wherein each twin memory cell includes first and second access transistors controlled by a wordline to connect first and second capacitors, with voltages representing complementary data values, to first and second bitlines, respectively; and

control circuitry configured to:

deactivate the wordline by lowering a wordline voltage of the wordline to a wordline off voltage, wherein the wordline off voltage is lower than a ground voltage of the memory device; and

precharge the plurality of first and second bitlines to a low voltage lower than the ground voltage of the memory device.

14. The memory device of claim 13 , wherein the control circuitry is further configured to:

access a twin memory cell, wherein accessing the twin memory cell comprises:

asserting the wordline voltage of the wordline which controls the first and second access transistors for the twin memory cell;

activating a sense amplifier connected to the first bitline and the second bitline for the twin memory cell, wherein the sense amplifier amplifiers a voltage difference between the first bitline and the second bitline, the voltage difference created by the voltages representing complementary data values.

15. The memory device of claim 14 , wherein a drive strength of the sense amplifier is increased by increasing a width of PMOS transistors of the sense amplifier with respect to other PMOS transistors in the memory device.

16. The memory device of claim 13 , further comprising:

a precharge voltage generator configured select the low voltage used to precharge the plurality of first and second bitlines.

17. The memory device of claim 13 , wherein a high voltage of the memory device applied to the bitlines by the plurality of senses amplifiers is decreased to compensate for a shortened retention time of the plurality of twin memory cells.

18. A method of accessing a twin cell memory device, wherein the memory device comprises a twin memory cell, wherein the twin memory cell stores a data value and a complement of the data value, and wherein the data value and the complement of the data value may be accessed via a first bitline and a second bitline of the memory device, respectively, the method comprising:

selecting a precharge voltage from a group of possible precharge voltages, the group comprising at least two of the following voltages:

a ground voltage, a wordline off voltage, and a back bias voltage; wherein the wordline off voltage and the back bias voltage are lower than the ground voltage;

precharging the first bitline and the second bitline to the selected precharge voltage;

asserting a wordline voltage to access the twin memory cell; and

sensing a voltage difference between the first and second bitline of the memory device, the voltage difference created by the data value and the complement of the data value.

19. A twin cell memory device comprising:

a first bitline and a second bitline;

a twin memory cell, wherein the twin memory cell stores a data value and a complement of the data value, and wherein the data value and the complement of the data value may be accessed via the first bitline and the second bitline,

circuitry configured to:

i) select a precharge voltage from a group of possible precharge voltages, the group comprising at least two of the following voltages:

a ground voltage, a wordline off voltage, and a back bias voltage; wherein the wordline off voltage and the back bias voltage are lower than the ground voltage;

precharge the first bitline and the second bitline to the selected precharge voltage;

ii) assert a wordline voltage to access the twin memory cell; and

iii) sense a voltage difference between the first and second bitline of the memory device, the voltage difference created by the data value and the complement of the data value.

20. The memory device of claim 13 , wherein the low voltage is one of the wordline off voltage and a back bias voltage, wherein the back bias voltage is a voltage applied to a substrate of the memory device.