Method for producing charge-trapping memory cell arrays

1. A method for producing a charge-trapping memory cell array, the method comprising:

providing a semiconductor body having a main surface;

applying a lower confinement layer of a first dielectric material over said semiconductor body;

applying a charge-trapping layer over said lower confinement layer;

applying an upper confinement layer of a second dielectric material over said charge-trapping layer;

after applying the upper confinement layer, performing a lithography step and a subsequent etching step to form trenches running parallel at a distance from one another at said main surface;

filling said trenches with a third dielectric material; and

after the filling the trenches, forming a wordline stack over the upper confinement layer.

2. The method according to claim 1 , wherein the semiconductor body comprises a silicon substrate.

3. The method according to claim 2 , wherein filling said trenches comprises filling said trenches with an oxide material by a selective oxidation of a surface of the silicon substrate.

4. The method according to claim 1 , wherein applying a charge-trapping layer comprises applying a silicon nitride layer.

5. The method according to claim 4 , wherein applying the lower confinement layer comprises applying a first oxide layer and wherein applying the upper confinement layer comprises applying a second oxide layer.

6. The method according to claim 1 , further comprising:

covering an area of said main surface that is provided for the memory cell array by a mask, after filling the trenches;

removing said upper confinement layer, said charge-trapping layer and said lower confinement layer in an area that is left free by said mask; and

applying a gate dielectric provided for transistors of an addressing circuitry onto said area that is left free by said mask.

7. The method according to claim 1 , further comprising, after filling said trenches, forming a plurality of wordlines over the main surface.

8. A method for producing a charge-trapping memory cell array, the method comprising:

providing a semiconductor body having a main surface;

applying a lower confinement layer of a first dielectric material over said main surface;

applying a charge-trapping layer over said lower confinement layer;

after applying the charge-trapping layer, performing a lithography step and a subsequent etching step to form trenches running parallel at a distance from one another at said main surface, wherein the lithography step is performed directly without deposition of a sacrificial oxide layer over the charge-trapping layer;

filling the trenches with a second dielectric material; and

concurrently with or after filling the trenches, forming an upper confinement layer over said charge-trapping layer.

9. The method according to claim 8 , wherein filling the trenches comprises depositing the second dielectric material in the trenches.

10. The method according to claim 9 , wherein depositing the second dielectric material in the trenches also forms the upper confinement layer.

11. The method according to claim 8 , wherein filling the trenches comprises growing the second dielectric material.

12. The method according to claim 11 , wherein the steps of filling the trenches and forming the upper confinement layer are performed by the growing of the dielectric material.

13. The method according to claim 8 , wherein applying a charge-trapping layer comprises applying a silicon nitride layer.

14. The method according to claim 8 , further comprising:

covering an area of said main surface that is provided for the memory cell array by a mask, after the forming the upper confinement layer;

removing said upper confinement layer, said charge-trapping layer and said lower confinement layer in an area that is left free by said mask; and

applying a gate dielectric provided for transistors of an addressing circuitry onto said area that is left free by said mask.

15. The method according to claim 8 , wherein the semiconductor body comprises a silicon substrate.

16. A method for producing a charge-trapping memory cell array, the method comprising:

providing a silicon substrate having a main surface;

applying a lower confinement layer of a first dielectric material onto said main surface;

applying a charge-trapping layer onto said lower confinement layer;

after the applying the charge-trapping layer, performing a lithography step and a subsequent etching step to form trenches running parallel at a distance from one another at said main surface, wherein the lithography step is performed directly without deposition of a sacrificial oxide layer over the charge-trapping layer;

filling said trenches by a selective oxidation of the silicon substrate;

after filling said trenches, forming an upper confinement layer on top of said charge-trapping layer; and

after forming the upper confinement layer, forming a wordline stack over the upper confinement layer.

17. The method according to claim 16 , wherein applying a charge-trapping layer comprises applying a silicon nitride layer.

18. The method according to claim 16 , further comprising:

covering an area of said main surface that is provided for the memory cell array by a mask, after forming the upper confinement layer;

removing said upper confinement layer, said charge-trapping layer and said lower confinement layer in an area that is left free by said mask; and

applying a gate dielectric provided for transistors of an addressing circuitry onto said area that is left free by said mask.

19. The method according to claim 16 , wherein forming the upper confinement layer comprises:

growing a second dielectric material.

20. The method according to claim 16 , wherein forming the upper confinement layer comprises:

depositing a second dielectric material.