Integrated circuit having resistive memory cells
View Patent ↗A memory includes an array of memory cells, each memory cell including resistive material, a first insulation material laterally surrounding the resistive material of each memory cell, and a heat spreader between the memory cells to thermally isolate each memory cell.
1. An integrated circuit comprising:
memory cells having resistive elements;
a first insulation material laterally surrounding the resistive elements; and
a heat spreader between the memory cells to distribute heat over the memory cells,
wherein the heat spreader comprises a second insulation material contacting the first insulation material, and
wherein the first insulation material has a lower thermal conductivity than the second insulation material.
2. The integrated circuit of claim 1 , wherein the first insulation material is selected from a group consisting of SiO 2 , porous SiO 2 , aerogel, xerogel, and a low-k dielectric.
3. The integrated circuit of claim 1 , wherein the second insulation material is selected from a group consisting of SiN, SiON, AlN, TiO 2 , and Al 2 0 3 .
4. The integrated circuit of claim 1 , wherein the resistive elements comprise phase-change material elements.
5. The integrated circuit of claim 1 , wherein the resistive elements are configured to increase in temperature in response to a write operation.
6. The integrated circuit of claim 1 , wherein the resistive elements comprise magnetic memory elements.
7. A memory comprising:
an array of resistive memory cells;
an insulation material having a first thermal conductivity around the resistive memory cells; and
lines of material having a second thermal conductivity greater than the first thermal conductivity between lines of the resistive memory cells for thermally isolating the resistive memory cells.
8. The memory of claim 7 , wherein the lines are selected from a group consisting of SiN, a metal, and poly-Si.
9. The memory of claim 7 , wherein the lines comprise electrical lines.
10. The memory of claim 7 , wherein the insulation material is selected from a group consisting of SiO 2 , BPSG, BSG, and a low-k dielectric.
11. The memory of claim 7 , wherein the resistive memory cells comprises phase-change memory cells.
12. A semiconductor memory device comprising:
an array of resistive memory cells;
a first material laterally surrounding the resistive memory cells; and
means for dissipating heat from each resistive memory cell during a write operation to prevent heating of adjacent resistive memory cells,
wherein the means comprises a second material contacting the first material, and
wherein the first material has a lower thermal conductivity than the second material.
13. The memory device of claim 12 , wherein the resistive memory cells comprise at least one of Ge, Sb, Te, Ga, As, In, Se, and S.