IP Library Granted Patent US 7,693,247
Granted Patent B2
US 7,693,247 · App. 11/238,331 · Granted Apr 6, 2010

Phase locked loop having reduced inherent noise

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Quick Facts
Patent No.
US 7,693,247
App. No.
11/238,331
Granted
Apr 6, 2010
Kind
B2
Abstract

A phase locked loop having reduced inherent noise is provided. The phase locked loop comprises a controlled oscillator for outputting a periodic output signal as a result of a control signal; a feedback unit for providing at least two periodic feedback signals having a constant phase shift to each other and each depending on the output signal; a phase/frequency detector for providing difference signals each depending on a periodic input signal and at least one of the feedback signals; and a control circuit for providing the control signal to the controlled oscillator depending on the difference signals.

Claims (50)

1. A phase locked loop, comprising:

a controlled oscillator for outputting a periodic output signal as a result of a control signal;

a feedback unit for providing at least two periodic feedback signals having a constant phase shift to each other, wherein each feedback signal depends on the output signal, and wherein the at least two periodic signals comprise an in-phase feedback signal which has no phase shift with respect to the output signal and a quadrature-phase feedback signal which has a 90° phase shift with respect to the output signal;

a frequency/phase detector for providing difference signals, each difference signal depending on a periodic input signal and at least one of the feedback signals; and

a control circuit for providing the control signal to the controlled oscillator depending on the difference signals, the control circuit comprising a charge pump that provides current pulses in response to the difference signals and adds the current pulses to provide a current output; wherein

at least one of the difference signals provided by the frequency/phase detector is a phase difference signal depending on the result of a comparison between one of the feedback signals and the input signal; and

at least one other of the difference signals provided by the frequency/phase detector is a frequency difference signal depending on the result of a comparison between one of the feedback signals and the input signal.

2. The phase locked loop of claim 1 , wherein the at least one of the difference signals provided by the frequency/phase detector that is a phase difference signal depending on the result of a comparison between one of the feedback signals and the input signal comprises two of the difference signals.

3. The phase locked loop of claim 1 , wherein the at least one other of the difference signals provided by the frequency/phase detector that is a frequency difference signal depending on the result of a comparison between one of the feedback signals and the input signal comprises two of the difference signals.

4. The phase locked loop of claim 1 , wherein the feedback unit comprises a frequency divider for dividing the frequency of the output signal.

5. The phase locked loop of claim 1 , wherein the control unit includes a weighting unit for weighing the current pulses prior to adding the pulses to provide the current output.

6. The phase locked loop of claim 5 , wherein the control unit includes a loop filter for receiving the weighed and added current pulses and for supplying a filtered control signal as the control input.

7. The phase locked loop of claim 6 , wherein the controlled oscillator is provided as a dual-loop-oscillator having a number of cascaded differential stages and a cross-connected control stage.

8. The phase locked loop of claim 7 , wherein each cascaded differential stage includes a controlled current source which is controlled to provide a coarse tuning of the oscillator.

9. The phase locked loop of claim 8 , wherein the cross-connected control stage includes a control transistor which is controlled depending on the control input signal.

10. The phase locked loop of claim 9 , wherein the cascaded differential stages and the cross-connected control stage each include an active load element.

11. The phase locked loop of claim 9 , wherein the cascaded differential stages and the cross-connected control stage each include a passive load resistor.

12. The phase locked loop of claim 7 , wherein each of the frequency/phase detector, the control unit, the loop filter, and the controlled oscillator is provided as a differential signaling circuit respectively.

13. The phase locked loop of claim 1 , wherein the controlled oscillator is provided as a digitally controlled oscillator.

14. A method for operating a phase locked loop, comprising:

outputting from a controlled oscillator a periodic signal as a result of a control signal;

providing via a feedback unit at least two periodic feedback signals having a constant phase shift to each other, wherein each feedback signal depends on the output signal, and wherein the feedback signals comprise:

an in-phase feedback signal which has no phase shift with respect to the output signal; and

a quadrature-phase feedback signal which has a 90° phase shift with respect to the output signal;

providing via a frequency/phase detector difference signals, each difference signal depending on a periodic input signal and at least one of the feedback signals; and

providing via a control circuit the control signal to the controlled oscillator depending on the difference signals, the control circuit providing current pulses via a charge pump in response to the difference signals and adds the current pulses to provide a current output; wherein

at least one of the difference signals provided by the frequency/phase detector is a phase difference signal depending on the result of a comparison between one of the feedback signals and the input signal; and

at least one other of the difference signals provided by the frequency/phase detector is a frequency difference signal depending on the result of a comparison between one of the feedback signals and the input signal.

15. The method of claim 14 , wherein the at least one of the difference signals that is a phase difference signal depending on the result of a comparison between one of the feedback signals and the input signal comprises two of the difference signals.

16. The method of claim 14 , wherein the at least one other of the difference signals that is a frequency difference signal depending on the result of a comparison between one of the feedback signals and the input signal comprises two of the difference signals.

17. The method of claim 16 , wherein the frequency of the output signal is divided.

18. The method of claim 14 , wherein the current pulses are weighed via a weighting unit prior to adding the pulses to provide the current output.

19. The method of claim 18 , wherein the weighed and added current pulses are filtered via a loop filter to supply a filtered control signal as the control input.

20. The method of claim 19 , wherein:

the controlled oscillator comprises a dual-loop-oscillator having a number of cascaded differential stages and a cross-connected control stage; and

the method further comprises:

controlling current in each of the cascaded differential stages; and

providing outputs of the cascaded differential stages to the cross-connected control stage.

21. The method of claim 20 , wherein the controlling current in each cascaded differential stage comprises controlling a controlled current source which is controlled to provide a coarse tuning of the oscillator.

22. The method of claim 21 , wherein:

the cross-connected control stage includes a control transistor; and

the method further comprises controlling the control transistor depending on the control signal.

23. The method of claim 22 , wherein:

the cascaded differential stages and the cross-connected control stage each include an active load element; and

the method further comprises controlling current in each of the cascaded differential stages via the active load element.

24. The method of claim 22 , wherein:

the cascaded differential stages and the cross-connected control stage each include a passive load resistor; and

the method further comprises controlling current in each of the cascaded differential stages via the passive load resistor.

25. The method of claim 20 , wherein each of the frequency/phase detector, the control unit, the loop filter, and the controlled oscillator function as differential signaling circuits.

26. The method of claim 14 , further comprising digitally controlling the oscillator.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 28, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036701/0926 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023773/0001 →