Memory device having low Vpp current consumption

1. A memory device comprising:

a memory bank;

a first group of cell blocks in the memory bank;

a second group of cell blocks in the memory bank, wherein each cell block of the first group shares at least one sense amplifier with a cell block of the second group; and

control circuitry configured to:

simultaneously activate each cell block of the first group while the cell blocks of the second group are left deactivated, wherein activating each cell block of the first group comprises connecting the cell block of the first group to the at least one sense amplifier shared with the second group;

while the cell blocks of the first group are activated and the cell blocks of the second group are deactivated, refresh each memory cell in the first group;

simultaneously activate each cell block of the second group while the cell blocks of the first group are left deactivated, wherein activating each cell block of the second group comprises connecting the cell block of the second group to the at least one sense amplifier shared with the first group; and

while the cell blocks of the second group are activated and the cell blocks of the first group are deactivated, refresh each memory cell in the second group.

2. The memory device of claim 1 , wherein each of the cell blocks in the first and second groups comprises memory cells accessed via local wordlines driven by master wordlines, and wherein refreshing each memory cell in the first and second groups comprises:

(a) activating a first local wordline selection signal for each master wordline in a cell block;

(b) sequentially activating each master wordline in the cell block while the first local wordline selection signal is activated;

(c) refreshing each memory cell accessed the first local wordline for each master word line in the cell block; and

repeating (a)-(c) for each local wordline for each master wordline in the cell block.

3. The memory device of claim 1 , wherein a precharge period during the self refresh is increased with respect to a precharge period during a read or write of the memory device.

4. The memory device of claim 1 , further comprising:

a data sense amplifier, wherein a signal used to connect the at least one sense amplifier with the data sense amplifier is lowered during a self refresh.

5. The memory device of claim 1 , further comprising:

a first access transistor between a bitline of the cell block of the first group and the at least one sense amplifier, wherein connecting each cell block of the first group to the at least one sense amplifier comprises asserting a first signal which activates the first access transistor; and

a second access transistor between a bitline of the cell block of the second group and the at least one sense amplifier, wherein connecting the each cell block of the second group to the at least one sense amplifier comprises asserting a second signal which activates the second access transistor.

6. A memory device comprising:

a means for banking memory;

a first group of cell blocks in the means for banking memory;

a second group of cell blocks in the means for banking memory, wherein each cell block of the first group shares at least one means for sensing with a cell block of the second group; and

means for controlling configured to:

simultaneously activate each cell block of the first group while the cell blocks of the second group are left deactivated, wherein activating each cell block of the first group comprises connecting the cell block of the first group to the at least one means for sensing shared with the second group;

while the cell blocks of the first group are activated and the cell blocks of the second group are deactivated, refresh each means for storing in the first group;

simultaneously activate each cell block of the second group while the cell blocks of the first group are left deactivated, wherein activating each cell block of the second group comprises connecting the cell block of the second group to the at least one means for sensing shared with the first group; and

while the cell blocks of the second group are activated and the cell blocks of the first group are deactivated, refresh each means for storing in the second group.

7. The memory device of claim 6 , wherein each of the cell blocks in the first and second groups comprises means for storing accessed via local wordlines driven by master wordlines, and wherein refreshing each means for storing in the first and second groups comprises:

(a) activating a first local wordline selection signal for each master wordline in a cell block;

(b) sequentially activating each master wordline in the cell block while the first local wordline selection signal is activated;

(c) refreshing each means for storing accessed the first local wordline for each master word line in the cell block; and

repeating (a)-(c) for each local wordline for each master wordline in the cell block.

8. The memory device of claim 6 , wherein a precharge period during the self refresh is increased with respect to a precharge period during a read or write of the memory device.

9. The memory device of claim 6 , further comprising:

a data means for sensing, wherein a signal used to connect the at least one means for sensing with the data means for sensing is lowered during a self refresh.

10. The memory device of claim 6 , further comprising:

a first means for accessing located between a bitline of the cell block of the first group and the at least one means for sensing, wherein connecting each cell block of the first group to the at least one means for sensing comprises asserting a first signal which activates the first means for accessing; and

a second means for accessing located between a bitline of the cell block of the second group and the at least one means for sensing, wherein connecting the each cell block of the second group to the at least one means for sensing comprises asserting a second signal which activates the second means for accessing.

11. A memory device comprising:

a row address counter;

one or more memory banks, wherein each memory bank comprises a plurality of alternating first and second cell blocks; and

control circuitry configured to:

receive a self refresh command;

perform a self refresh comprising:

refreshing each row of memory cells in the first cell blocks when a most significant bit of the row address counter is a first value;

refreshing each row of memory cells in the second cell blocks when the most significant bit of the row address counter is a second value; and

incrementing the counter after each row of memory cells is refreshed.

12. The memory device of claim 11 , wherein each row of memory cells comprises memory cells accessed via local wordlines driven by master wordlines, and wherein the access control circuitry is further configured to:

(a) activate a first local wordline selection signal for each master wordline in a cell block;

(b) sequentially activate each master wordline in the cell block while the first local wordline selection signal is activated;

(c) refresh each memory cell accessed the first local wordline for each master wordline in a cell block; and

repeat (a)-(c) for each local wordline for each master wordline in the cell block.

13. The memory device of claim 11 , wherein each first cell block and each second cell block share a bitline sense amplifier with an adjacent second cell block and first cell block, respectively.

14. The memory device of claim 13 , wherein the access control circuitry is configured to:

connect each of the first cell blocks to the shared bitline sense amplifier when the most significant bit of the row address counter is the first value; and

connect each of the second cell blocks to the shared bitline sense amplifier when the most significant bit of the row address counter is the second value.

15. The memory device of claim 11 , further comprising:

circuitry configured to:

determine if a cell block contains a defective wordline;

if the cell block is one of the first cell blocks, replace the defective wordline with a redundant wordline in another one of the first cell blocks; and

if the cell block is one of the second cell blocks, replace the defective wordline with a redundant wordline in another one of the second cell blocks.

16. A memory device comprising:

a refresh circuit comprising a row address counter and a self refresh timer;

one or more memory banks, wherein each memory bank comprises a plurality of alternating first and second cell blocks;

wiring circuitry configured to:

receive an address provided by the row address counter from the row address multiplexer during a self refresh; and

output bits of the row address counter as a modified row address, wherein the modified row address is used to refresh memory cells in the first cell blocks during a first portion of the self refresh and refresh memory cells in the second cell blocks during the second portion of the self refresh; and

control circuitry configured to perform the self refresh by:

incrementing the counter row address counter using the self refresh timer, until each memory cell in the one or more memory banks is refreshed.

17. The memory device of claim 16 , wherein the modified row address is further configured to:

(a) activate a first local wordline selection signal for each master wordline in a cell block;

(b) sequentially activate each master wordline in the cell block while the first local wordline selection signal is activated;

(c) refresh each memory cell accessed the first local wordline for each master wordline in a cell block; and

repeat (a)-(c) for each local wordline for each master wordline in the cell block.