Memory having parity error correction
View Patent ↗A memory includes a sense amplifier segment and a plurality of word lines including a spare word line, a first transfer word line, and a second transfer word line complementary to the first transfer word line. The memory includes a plurality of bit lines coupled to the sense amplifier segment and a memory cell located at each cross point of each word line and each bit line. The first transfer word line and the second transfer word line are adapted for simultaneously inverting data bit values stored in memory cells along a failed word line to correct a parity error during self refresh.
1. A memory comprising:
a sense amplifier segment;
a plurality of word lines including a spare word line, a first transfer word line, and a second transfer word line complementary to the first transfer word line;
a plurality of bit lines coupled to the sense amplifier segment; and
a memory cell located at each cross point of each word line and each bit line,
wherein the first transfer word line and the second transfer word line are adapted for simultaneously inverting data bit values stored in memory cells along a failed word line to correct a parity error during self refresh.
2. The memory of claim 1 , wherein the spare word line is adapted to replace a failed word line during self refresh due to a parity error.
3. The memory of claim 1 , wherein the first transfer word line and the second transfer word line are adapted to correct parity errors without knowing a location of a failed memory cell along the failed word line.
4. The memory of claim 1 , wherein the plurality of word lines comprises true word lines and complement word lines.
5. The memory of claim 1 , wherein the plurality of bit lines comprises true bit lines and complement bit lines.
6. A memory comprising:
a sense amplifier segment;
a plurality of word lines including a spare word line, a first transfer word line, and a second transfer word line;
a plurality of bit lines coupled to the sense amplifier segment; and
a memory cell located at each cross point of each word line and each bit line,
wherein a memory cell located along the first transfer word line coupled to a first sense amplifier is electrically shorted to a memory cell located along the second transfer word line coupled to the sense amplifier for inverting data bit values stored in memory cells along a failed word line to correct a parity error during self refresh.
7. The memory of claim 6 , wherein the spare word line is adapted to replace a failed word line during self refresh due to a parity error.
8. The memory of claim 6 , wherein the first transfer word line and the second transfer word line are adapted to correct parity errors without knowing a location of a failed memory cell along the failed word line.
9. The memory of claim 6 , wherein the plurality of word lines comprises true word lines and complement word lines.
10. The memory of claim 6 , wherein the plurality of bit lines comprises true bit lines and complement bit lines.
11. A dynamic random access memory comprising:
a sense amplifier bank including a plurality of sense amplifiers;
a true bit line coupled to a first input of each sense amplifier;
a complement bit line coupled to a second input of each sense amplifier;
a plurality of word lines including a spare word line for replacing a failed word line due to a parity error detected during self refresh, and a first transfer word line and a second transfer word line; and
a plurality of memory cells, each memory cell located at a cross point of each word line and each true bit line and complement bit line,
wherein the memory cell located along the first transfer word line at the cross point of each true bit line is electrically shorted to the memory cell located along the second transfer word line at the cross point of each complement bit line for each sense amplifier, and
wherein the first transfer word line and the second transfer word line are adapted for simultaneously inverting data bit values stored in memory cells along a failed word line for correcting for a parity error detected during self refresh.
12. The memory of claim 11 , wherein the first transfer word line and the second transfer word line are adapted to correct parity errors without knowing a location of a failed memory cell along the failed word line.
13. A memory comprising:
means for replacing a failed word line with a spare word line during self refresh due to a parity error detected during self refresh without affecting self refresh timing; and
means for simultaneously inverting data bit values stored in memory cells along the failed word line to correct for the parity error during self refresh.
14. The memory of claim 13 , further comprising:
means for mapping an address of the failed word line to the spare word line.
15. A memory comprising:
a sense amplifier segment;
a plurality of word lines including a spare word line, a first transfer word line, and a second transfer word line complementary to the first transfer word line;
a plurality of bit lines coupled to the sense amplifier segment; and
a memory cell located at each cross point of each wordline and each bit line,
wherein a memory cell along the first transfer word line is electrically shorted to a memory cell along the second transfer word line, and
wherein the first transfer word line and the second transfer word line are adapted for simultaneously inverting data bit values stored in memory cells along a failed word line to correct a parity error during self refresh.
16. The memory of claim 15 , wherein the spare word line is adapted to replace a failed word line during self refresh due to a parity error.
17. The memory of claim 15 , wherein the first transfer word line and the second transfer word line are adapted to correct parity errors without knowing a location of a failed memory cell along the failed word line.
18. The memory of claim 15 , wherein the plurality of word lines comprises true word lines and complement word lines.
19. The memory of claim 15 , wherein the plurality of bit lines comprises true bit lines and complement bit lines.
20. A memory comprising:
means for replacing a failed word line with a spare word line during self refresh due to a parity error detected during self refresh without affecting self refresh timing; and
means for simultaneously inverting data bit values stored in memory cells along the failed word line to correct for the parity error during self refresh,
wherein the means for simultaneously inverting data bit values stored in memory cells along the failed word line comprises a memory cell along a first transfer word line electrically shorted to a memory cell along a second transfer word line.
21. The memory of claim 20 , further comprising:
means for mapping an address of the failed word line to the spare word line.