Method for fabricating a semiconductor component and semiconductor component

1. A method for fabricating an integrated circuit having a component, comprising:

providing a substrate comprising a first surface;

forming a mold on said first surface, said mold comprising at least one depression arranged in such a way that a contact region in a region of said first surface is at least partly uncovered, and wherein the depression comprises a lower section abutting the first surface and an upper section overlying the lower section and remote from the first surface;

forming a sacrificial layer on sidewalls of said depression in solely the upper section of said depression, wherein the lower section of the depression is not covered with the sacrificial layer;

forming a first electrode by applying a first conductive layer in the lower section of said depression and to said sacrificial layer in the upper section of said depression;

removing said sacrificial layer in order to uncover said sidewalls of said mold in said upper section;

applying a dielectric layer to said first conductive layer; and

forming a second electrode by applying a second conductive layer to said dielectric layer.

2. The method of claim 1 , wherein said depression comprises, in a region of said upper section, a cross section that decreases in a direction toward said first surface.

3. The method of claim 1 , wherein applying the sacrificial layer comprises applying said sacrificial layer with a thickness that decreases in a direction toward said first surface.

4. The method of claim 1 , wherein applying the sacrificial layer comprises applying said sacrificial layer by means of an atomic layer deposition method.

5. The method of claim 1 , further comprising, prior to applying said dielectric layer, removing said mold only in said upper section.

6. The method of claim 1 , further comprising, after applying said sacrificial layer and prior to applying said first conductive layer, etching said sidewalls of the mold in said lower section of the depression, which are not covered by said sacrificial layer.

7. The method of claim 1 , wherein said component is a capacitor device for a semiconductor memory.

8. The method of claim 1 , wherein producing the first electrode results in the first electrode having an inwardly facing surface opposite the depression and the sacrificial layer, and wherein removing the sacrificial layer exposes an outwardly facing surface of the first electrode in the upper section of the depression, and wherein applying the dielectric layer results in the dielectric layer overlying both the inwardly facing surface and the outwardly facing surface of the first electrode.

9. The method of claim 8 , wherein forming the second electrode comprises overlying the dielectric layer in regions corresponding to both the inwardly facing surface and the outwardly facing surface of the first electrode.

10. A method of forming an integrated circuit comprising a capacitor, comprising:

forming a mold over a first surface of a substrate;

forming a depression in the mold to uncover a contact region, the contact region being disposed in a region of the first surface;

forming a sacrificial layer after forming the depression, the sacrificial layer covering a sidewall of an upper section of the depression, and leaving a lower section of the depression uncovered with respect to the sacrificial layer;

forming a conductive layer over the lower and the upper sections of the depression, thereby forming a first electrode;

removing the sacrificial layer;

forming a dielectric layer over the first electrode; and

forming a second conductive layer over the dielectric layer to form a second electrode.