Semiconductor memory arrangement with branched control and address bus
View Patent ↗A semiconductor memory arrangement for operation in a data memory system with at least one semiconductor memory chip for the storage of user data includes a memory controller for control of the at least one semiconductor memory chip, and at least one unidirectional signal line bus for control and address signals connected with the memory controller and branching at least once. The at least once branching bus directly connecting at least one semiconductor memory chip with the memory controller and connecting the semiconductor memory chips among each other.
1. A semiconductor memory arrangement for operation in a data memory system comprising:
at least one semiconductor memory chip for the storage of user data;
a memory controller for control of the at least one semiconductor memory chip; and
at least one unidirectional signal line bus for control and address signals connected with the memory controller and branching at least once, the at least once branching bus directly connecting at least one semiconductor memory chip with the memory controller and connecting the semiconductor memory chips among each other.
2. The semiconductor memory arrangement according to claim 1 , wherein the signal line bus for control and address signals includes 1-point-to-in-point connections, whereby m is a natural number in the range of 1 to 4.
3. The semiconductor memory arrangement according to claim 1 , wherein the at least one signal line bus for control and address signals branches to directly connect the memory controller to at least two semiconductor memory chips.
4. The semiconductor memory arrangement according to claim 3 , wherein the at least one signal line bus for control and address signals serially connects the semiconductor memory chips of each branch with each other in a non-branched fashion.
5. The semiconductor memory arrangement according to claim 1 , wherein the at least one signal line bus for control and address signals connects the semiconductor memory chips with each other by a tree-like branching structure.
6. The semiconductor memory arrangement according to claim 1 , further comprising:
at least one signal line bus for read data, wherein the signal line bus for read data directly connects one of the semiconductor memory chips to the memory controller and serially connects the semiconductor memory chips with each other by 1-point-to-1-point connections.
7. The semiconductor memory arrangement according to claim 1 , wherein at least one of the semiconductor memory chips is provided with a re-drive unit for re-driving of control and address signals.
8. The semiconductor memory arrangement according to claim 1 , wherein at least one of the semiconductor memory chips includes an evaluation unit for evaluating control and address signals.
9. The semiconductor memory arrangement according to claim 1 , wherein at least one of the semiconductor memory chips includes a re-drive unit for re-driving of read signals.
10. The semiconductor memory arrangement according to claim 1 , further comprising:
at least one signal line bus for write data, wherein the signal line bus for write data directly connects one of the semiconductor memory chips to the memory controller and serially connects the semiconductor memory chips with each other by 1-point-to-1-point connections.
11. The semiconductor memory arrangement according to claim 10 , wherein at least one of the semiconductor memory chips includes a re-drive unit for re-driving of write signals.
12. The semiconductor memory arrangement according to claim 1 , wherein a signal line bus for control and address signals is allocated to at least one rank.
13. The semiconductor memory arrangement according to claim 12 , wherein a signal line bus for control and address signals is allocated to two or four ranks.
14. The semiconductor memory arrangement according to claim 1 , wherein a signal line bus for control and address signals is allocated to at least one lane.
15. The semiconductor memory arrangement according to claim 14 , wherein a signal line bus for control and address signals is allocated to more than one lane.
16. The semiconductor memory arrangement according to claim 1 , wherein a signal line bus for read data is allocated to one lane.
17. The semiconductor memory arrangement according to claim 1 , wherein a signal line bus for write data is allocated to one lane.
18. The semiconductor memory arrangement according to claim 1 , wherein at least one signal line bus selected from the group consisting of a signal line bus for control and address signals, a signal line bus for write signals and a signal line bus for read signals, is comprised of differential signal line pairs.
19. The semiconductor memory arrangement according to claim 1 , wherein at least one signal line bus selected from the group consisting of a signal line bus for control and address signals, a signal line bus for write signals and a signal line bus for read signals, is combined with a signal line bus for clock signals.
20. The semiconductor memory arrangement according to claim 1 , wherein at least two signal line bus selected from the group consisting of a signal line bus for control and address signals, a signal line bus for write signals and a signal line bus for read signals, are combined with each other.
21. The semiconductor memory arrangement according to claim 1 , wherein the semiconductor memory chips are provided in the form of DRAM semiconductor memory chips.
22. The semiconductor memory arrangement according to claim 21 , wherein the semiconductor memory chips each include a DDR interface.
23. The semiconductor memory arrangement according to claim 1 , wherein the semiconductor memory arrangement is arranged on a semiconductor memory module.
24. The semiconductor memory arrangement according to claim 1 , wherein the semiconductor memory module is DIMM semiconductor memory module.
25. The semiconductor memory arrangement according to claim 23 , further comprising:
a semiconductor memory module with semiconductor memory chips arranged on a front and a back side;
one signal line bus for control and address data connected to the semiconductor memory chips on the front side of the semiconductor memory module; and
an additional signal line bus for control and address data connected to the semiconductor memory chips on the back side of the semiconductor memory module.
26. A data memory system, comprising:
a plurality of semiconductor memory arrangements, individual ones of the semiconductor memory arrangements comprising:
at least one semiconductor memory chip for the storage of user data;
a memory controller for control of the at least one semiconductor memory chip; and
at least one unidirectional signal line bus for control and address signals connected with the memory controller and branching at least once, the at least once branching bus directly connecting at least one semiconductor memory chip with the memory controller and connecting the semiconductor memory chips among each other.