Memory having parity generation circuit

1. A memory comprising:

a column segment comprising memory cells along word lines; and

a parity generation circuit configured to receive a first serial data stream of data bit values stored in memory cells along a word line and determine a first parity value of the first serial data stream upon entry of self refresh,

wherein the parity generation circuit is configured to pass the first parity value of the first serial data stream to the column segment to store the first parity value in a memory cell along the word line, and

wherein the parity generation circuit is configured to receive a second serial data stream of data bit values stored in the memory cells along the word line after at least one self refresh interval and determine a second parity value of the second serial data stream during self refresh.

2. The memory of claim 1 , further comprising:

a parity compare circuit configured to compare the first parity value to the second parity value and provide a parity mismatch signal based on the comparison.

3. The memory of claim 1 , further comprising:

a sense amplifier and input/output circuit configured to provide the first serial data stream in response to a column select line burst.

4. A memory comprising:

a column segment comprising memory cells along word lines; and

a parity generation circuit configured to receive a first serial data stream of data bit values stored in memory cells along a word line and determine a first parity value of the first serial data stream upon entry of self refresh.

wherein the parity generation circuit is configured to determine the first parity value by toggling a bit in response to each logic high data bit value in the first serial data stream.

5. A memory comprising:

a column segment comprising memory cells along word lines;

a parity generation circuit configured to determine the parity of data bit values stored in memory cells along each word line based on serial data streams of data bit values stored in memory cells along each word line;

a parity compare circuit configured to compare stored parity values for each word line to current parity values for each word line; and

a control circuit configured to provides signals to the column segment, parity generation circuit, and parity compare circuit to:

generate first parity values of data bit values stored in memory cells along each word line upon entry to self refresh and store the first parity values;

generate second parity values of data bit values stored in the memory cells along each word line during self refresh; and

compare the first parity values to the second parity values to detect errors.

6. The memory of claim 5 , wherein the parity generation circuit is configured to determine the parity of data bit values stored in memory cells along each word line based on the serial data streams by toggling a bit in response to each logic high data bit value in each serial data stream.

7. The memory of claim 5 , wherein the parity compare circuit comprises an XOR gate for comparing the first parity values for each word line to the second parity values for each word line.

8. The memory of claim 5 , wherein the column segment comprises memory cells for storing the first parity values.

9. The memory of claim 5 , wherein the control cfrcuit is configured to provide column select line burst signals to the column segment to provide each serial data stream of data bit values stored in memory cells along each word line.

10. A dynamic random access memory comprising:

an array of memory cells comprising word lines and bit lines;

a parity circuit configured to determine first parity values of data bit values stored in memory cells along each word line upon self refresh entry, periodically determine second parity values of data bit values stored in the memory cells along each word line during self refresh, and compare the first parity values to the second parity values for each word line to check for errors in the array of memory cells; and

a control circuit configured to provide column select line bursts to provide a serial data stream of data bit values stored in memory cells along each word line to the parity circuit for determining the first parity values and the second parity values for each word line.

11. The memory of claim 10 , wherein the parity circuit is configured to toggle a bit in response to each logic high data bit value in each serial data stream to determine the first parity values and the second parity values for each word line.

12. The memory of claim 10 , wherein the memory comprises a low power dynamic random access memory.

13. The memory of claim 10 , wherein the memory comprises a CellularRAM.

14. A dynamic random access memory comprising:

a column segment comprising memory cells along word lines;

means for receiving a first serial data stream of data bit values stored in memory cells along a word line to determine a first parity value of the first serial data stream upon entry of self refresh, and

means for storing the first parity value in a memory cell atone the word line,

wherein the means for receiving further comprises means for receiving a second serial data stream of data bit values stored in the memory cells along the word line after at least one self refresh interval to determine a second parity value of the second serial data stream during self refresh.

15. The memory of claim 14 , further comprising:

means for comparing the first parity value to the second parity value to provide a parity mismatch signal based on the comparison.

16. The memory of claim 14 , further comprising:

means for providing the first serial data stream in response to a column select line burst.

17. A method of checking for errors in a memory, the method comprising:

providing a first serial data stream upon self refresh entry, the first serial data stream comprising data bit values stored in memory cells along a word line in a column segment;

generating a first parity value for the data bit values stored in the memory cells based on the first serial data stream;

storing the first parity value;

providing a second serial data stream comprising data bit values stored in the memory cells along the word line during self refresh;

generating a second parity value for the data bit values stored in the memory cells based on the second serial data stream; and

comparing the first parity value to the second parity value.

18. The method of claim 17 , further comprising:

correcting for a parity error if the first parity value does not equal the second parity value.

19. The method of claim 17 , wherein providing the first serial data stream comprises providing a column select line burst to output the data bit values stored in the memory cells along the word line on a local data line.

20. A method of checking for errors in a memory, the method comprising:

providing a first serial data stream of data bit values stored in memory cells along a word line upon entry to self refresh;

determining a first parity value of the first serial data stream by toggling a parity bit in response to each logic high data bit value in the first serial data stream;

providing a second serial data stream of data bit values stored in the memory cells along the word line during self refresh;

determining a second parity value of the second serial data stream by toggling the parity bit in response to each logic high data bit value in the second serial data stream; and comparing the first parity value to the second parity value.

21. The method of claim 20 , further comprising:

storing the first parity value in a memory cell along the word line.

22. The method of claim 20 , further comprising:

providing a column select line burst,

wherein the first serial data stream is provided in response to the column select line burst.

23. The method of claim 20 , further comprising:

correcting for a parity error if the first parity value does not equal the second parity value.

24. A method of checking for errors in a dynamic random access memory, the method comprising:

generating a first column select line burst upon entry to self refresh;

providing a first serial data stream for each column segment of data bit values stored in memory cells along a word line in each column segment in response to the first column select line burst;

determining a first parity value of the first serial data stream for each column segment by toggling a parity bit for each column segment in response to each logic high data bit value in each first serial data stream;

generating a second column select line burst during self refresh;

providing a second serial data stream for each column segment of data bit values stored in the memory cells along the word line in each column segment in response to the second column select line burst;

determining a second parity value of the second serial data stream for each column segment by toggling the parity bit for each column segment in response to each logic high data bit value in each second serial data stream; and

comparing the first parity value to the second parity value for each column segment to check for errors.

25. The method of claim 24 , further comprising:

correcting for a parity error if the first parity value does not equal the second parity value for each column segment.