Controllable delay device

1. A circuit arrangement for controllably delaying electrical signals between a circuit input and at least one circuit output, comprising:

a first delay chain having n series-connected delay elements, each of which comprising an active circuit with a fixed transit time, wherein an input of a first delay element is connected to the circuit input, wherein an output of each delay element is selectively connectable to a forwarding circuit leading to a first circuit output via a respectively associated switch of a first group of switches, wherein the forwarding circuit has a second delay chain leading to the first circuit output, the second delay chain comprising n series-connected delay elements, each of which comprising an active circuit with a fixed transit time, and wherein the output of each delay element of the first delay chain is selectively connectable to a respective input of the (n−i+1)th delay element of the second delay chain via the respectively associated switch of the first group of switches, wherein i=1 . . . n is defined as an ordinal number of the delay elements of the first delay chain,

wherein the forwarding circuit has a third delay chain, leading to a second circuit output, with n +1 series-connected delay elements, each of which comprising an active circuit with a fixed transit time,

wherein an input of a last delay element of the third delay chain is connectable to the circuit input via an associated switch of a second group of switches, and

wherein the output of each delay element of the first delay chain is selectively connectable to a respective input of the (n−i+1)th delay element of the third delay chain via a respectively associated other switch of the second group of switches.

2. The circuit arrangement as claimed in claim 1 , wherein the circuit input is connected to an additional load impedance which is equal to an input impedance of each delay element of the delay chains.

3. The circuit arrangement as claimed in claim 2 , wherein the additional load impedance comprises a further delay element which is substantially identical with the delay elements of the delay chains.

4. The circuit arrangement as claimed in claim 1 , wherein an output of the last delay element of the first delay chain is connected to an additional load impedance which is equal to the input impedance of each delay element of the delay chains.

5. The circuit arrangement as claimed in claim 4 , wherein the additional load impedance comprises a further delay element which is substantially identical with the delay elements of the delay chains.

6. The circuit arrangement as claimed in claim 1 , wherein a spatially parallel arrangement, an orientation of the delay chains relative to one another, and line runs between the delay chains are arranged such that all connections between the delay chains span about the same spatial distance and have about the same line length.

7. The circuit arrangement as claimed in claim 1 , wherein all connections between the delay chains have about the same transit time τ Q .

8. The circuit arrangement as claimed in claim 7 , wherein all delay elements of the first delay chain and all delay elements except the respective last delay element of each delay chain of the forwarding circuit have about the same transit time τ E , and wherein the transit time of the respective last delay element of each delay chain of the forwarding circuit is equal to τ E −τ Qi , wherein τ Qi is a transit time between a respective connection between the delay chains.

9. The circuit arrangement as claimed in claim 1 , wherein all delay elements of the delay chains have about the same transit time τ E .

10. A system, comprising the circuit arrangement of claim 1 and a plurality of electrical components, the plurality of electrical components being at least one of structurally and functionally related.

11. The system of claim 10 , wherein at least one of the plurality of electrical components is a delay-locked loop (DLL).

12. A circuit arrangement for controllably delaying electrical signals between a circuit input and a first and a second circuit output, comprising:

a first delay chain having n series-connected delay elements;

a second delay chain having n series-connected delay elements;

a third delay chain having n+1 series-connected delay elements;

wherein each of the delay elements of the first, second and third delay chains comprises an active circuit with a fixed transit time and has an input and an output,

wherein an input of a first delay element of the first delay chain is connected to the circuit input,

wherein an output of an n-th delay element of the second delay chain is connected to the first circuit output,

wherein an output of an (n+1)-th delay element of the third delay chain is connected to the second circuit output,

wherein an output of an i-th delay element of the first delay chain is selectively connected to an input of an (n−i+1)-th delay element of the second delay chain via a respectively associated switch of a first group of switches,

wherein the output of the i-th delay element of the first delay chain is selectively connected to an input of an (n−i+1)-th delay element of the third delay chain via a respectively associated switch of a second group of switches,

wherein an input of the (n+1)-th delay element of the third delay chain is connected to the circuit input via an associated switch of the second group of switches,

wherein i=1 . . . n is defined as an ordinal number of the delay elements of the first, second and third delay chains.

13. The circuit arrangement as claimed in claim 12 , wherein the circuit input is connected to an additional load impedance which is equal to the input impedance of each delay element of the delay chains.

14. The circuit arrangement as claimed in claim 13 , wherein the additional load impedance comprises a further delay element which is substantially identical with the delay elements of the delay chains.

15. The circuit arrangement as claimed in claim 12 , wherein a spatially parallel arrangement, an orientation of the delay chains relative to one another, and line runs between the delay chains, are arranged such that all connections between the delay chains span about the same spatial distance and have about the same line length.

16. The circuit arrangement as claimed in claim 12 , wherein all connections between the delay chains have about the same transit time τ Q .

17. The circuit arrangement as claimed in claim 12 , wherein all delay elements of the delay chains have about the same transit time τ E .

18. The circuit arrangement as claimed in claim 12 , wherein all delay elements of the first delay chain and all delay elements except the respective last delay element of each delay chain of the forwarding circuit have about the same transit time τ E , and wherein the transit time of the respective last delay element of each delay chain of the forwarding circuit is equal to τ E −τ Qi , wherein τ Qi is a transit time between a respective connection between the delay chains.

19. A system, comprising arrangement of claim 12 and a plurality of electrical components, the plurality of electrical components being at least one of structurally and functionally related.

20. The system of claim 19 , wherein at least one of the plurality of electrical components is a delay-locked loop (DLL).

21. A controllable delay circuit, comprising:

a first delay chain having a signal input, the first delay chain comprising a first plurality of series-connected delay elements, each delay element having an output tap;

a second delay chain having a signal output, the second delay chain comprising a second plurality of series-connected delay elements and a corresponding plurality of switches connected to a respective input of each delay element of the second delay chain, wherein each switch is controllably switched to connect to one of an output of the delay elements in the first delay chain in reverse order and an output of a preceding delay element of the second delay chain, if present; and

a third delay chain having a second signal output, the third delay chain comprising a third plurality of series-connected delay elements and a corresponding plurality of switches connected to a respective input of each delay element of the third delay chain, wherein each switch is controllably switched to connect to one of an output of the delay elements in the first delay chain in reverse order and an output of preceding delay element of the third delay chain, if present, wherein the third delay chain comprises one additional delay element than the second delay chain, wherein the one additional delay element is switchably connected between an output of preceding delay element of the third delay chain and the signal input, and wherein the one additional delay element is connected to provide the second signal output.

22. The controllable delay circuit of claim 21 , further comprising:

a first additional load impedance connected to the signal input; and

a second additional load impedance connected to an output of a last delay element of the first delay chain;

wherein each additional load impedance comprises a further delay element which is substantially identical with the delay elements of the delay chains.

23. A system, comprising the controllable delay circuit of claim 21 and a plurality of electrical components, the plurality of electrical components being at least one of structurally and functionally related.

24. The system of claim 23 , wherein at least one of the plurality of electrical components is a delay-locked loop (DLL).