Memory device and method of manufacturing a memory device
View Patent ↗The invention relates to a method of forming a memory device comprising a memory cell array and a peripheral portion. When forming the capacitors in the memory cell array, a sacrificial layer is deposited which is usually made of silicon dioxide and which is used for defining the storage electrode above the substrate surface. The sacrificial layer is removed selectively from the array portion while being maintained in the peripheral portion. This is achieved by providing an array separation trench which acts as a lateral etch stop.
1. A method of forming an integrated circuit comprising a plurality of storage capacitors, the method comprising:
providing a sacrificial layer covering a substrate surface of a semiconductor substrate;
defining openings in the sacrificial layer, each opening exposing an array contact pad formed in an array portion of the semiconductor substrate;
defining peripheral contact openings in the sacrificial layer, each peripheral contact opening exposing a part of a peripheral circuitry formed in a peripheral portion of the semiconductor substrate;
thereafter providing a storage electrode of a first conductive material in each of the openings in the array portion so that each storage electrode is in contact with one of the array contact pads;
masking the peripheral portion with a layer of a second masking material which is different from a material of the sacrificial layer;
removing the sacrificial layer from the array portion while maintaining the sacrificial layer in the peripheral portion;
providing a storage dielectric on each storage electrode;
thereafter removing the second masking material; and
thereafter providing a counter electrode on each storage dielectric in the array portion thereby completing the plurality of storage capacitors and a second conductive material in the peripheral contact openings so as to complete a plurality of peripheral contacts.
2. The method of claim 1 , wherein
the openings and the peripheral contact openings are formed simultaneously by one step of etching the sacrificial layer.
3. The method of claim 1 , further comprising:
defining an array separation trench in the sacrificial layer at a boundary region separating the array portion and the peripheral portion; and
filling the array separation trench at least partially with a first masking material which is different from the material of the sacrificial layer.
4. The method of claim 1 , wherein providing the storage electrodes comprises;
depositing a conductive liner layer on a surface of the sacrificial layer and a surface of the openings and a surface of the peripheral contact openings after defining the openings and the peripheral contact openings.
5. The method of claim 4 , further comprising
depositing a further sacrificial layer in the peripheral contact openings after depositing the conductive liner layer.
6. The method of claim 1 , further comprising
providing a plurality of peripheral contact pads connected with at least part of the peripheral circuitry, wherein each of the peripheral contact openings is in contact with one of the peripheral contact pads.
7. The method of claim 1 , wherein the second conductive material in the peripheral contact openings comprises tungsten.
8. The method of claim 4 , further comprising removing the conductive liner layer from the peripheral contact openings.