Semiconductor memory device

1. An integrated circuit including a semiconductor memory device comprising a plurality of memory cells, wherein each memory cell comprises a respective transistor, said transistor comprises:

a transistor body of a first conductivity type, wherein the transistor body is electrically isolated from transistor bodies of neighboring memory cells;

a drain area and a source area each having a second conductivity type, said drain area and source area are embedded in the transistor body on a first surface of said transistor body;

a gate structure having a gate dielectric layer and a gate electrode, wherein said gate structure is arranged between said drain area and said source area;

an emitter area of said first conductivity type, wherein said emitter area is operably associated with said drain area; and

at least one bit line and at least one source line, wherein said source area is connected to said source line, and said emitter area is connected directly to said bit line through a bit line contact.

2. The integrated circuit according to claim 1 , further comprising a semiconductor substrate of said second conductivity type, wherein said transistor body is arranged adjacent to said semiconductor substrate.

3. The integrated circuit according to claim 1 , wherein said transistor body comprises a first region and a second region, wherein said second region is arranged near said first surface and said first region is arranged in a bulk area of the transistor body under and adjacent to said second region, wherein a doping concentration of dopants of said first conductivity type is higher in said first region than in said second region.

4. The integrated circuit according to claim 1 , wherein said emitter area is distanced from said gate electrode by said gate dielectric layer.

5. The integrated circuit according to claim 1 , wherein the emitter area is adjacent to the drain area.

6. The integrated circuit according to claim 1 , further comprising a recess formed in said first surface between said drain area and said source area, wherein said gate dielectric layer and said gate electrode are at least partially arranged in said recess.

7. The integrated circuit according to claim 6 , wherein a vertical extension of said recess is larger than a vertical extension of said drain area and/or said source area.

8. The integrated circuit according to claim 1 , further comprising an underlying semiconductor substrate and an isolation layer wherein said transistor body is isolated from said underlying semiconductor substrate by said isolation layer.

9. The integrated circuit according to claim 8 , wherein the transistor body further comprises a third region and a vertical border, wherein said third region is arranged adjacent to both said semiconductor substrate and said vertical border, and wherein a doping concentration of a dopant of said first conductivity type is higher in said third region than in said bulk area of the transistor body.

10. The integrated circuit according to claim 1 , further comprising at least one word line, wherein said gate electrode is connected to said word line, and said drain area is connected to said bit line.

11. The integrated circuit according to claim 10 , wherein said source line is formed as a spacer, and wherein said spacer is arranged adjacent to said gate electrode.

12. The integrated circuit according to claim 1 , further comprising an isolation trench arranged adjacent to and surrounding one or more sidewalls of said transistor body.

13. The integrated circuit according to claim 12 , further comprising a conductive material and a dielectric layer at least partially filling said isolation trench, wherein said dielectric layer is arranged on sidewalls of said isolation trench for isolating said transistor body from said conductive material.

14. The integrated circuit according to claim 13 , wherein the conductive material forms a first common electrode of said plurality of memory cells.

15. An integrated circuit formed on a substrate, comprising:

a source region having a first conductivity type;

a drain region having the first conductivity type;

a body region having a second conductivity type opposite to the first conductivity type, the body region extending to a first depth below the substrate surface, the body region comprising a channel region extending between the source region and drain region;

a gate electrode adjacent to the channel region, and a gate dielectric disposed between the gate electrode and the channel region;

an emitter region having the second conductivity type arranged adjacent to or embedded in the drain region, the emitter region separated from the body region by the drain region;

an isolation region directly under the body region; and

an isolation trench comprising a dielectric material, the isolation trench laterally surrounding the body region and extending downward to a second depth below the substrate surface, wherein the second depth is larger than the first depth.

16. The semiconductor device of claim 15 , wherein the isolation region comprises a semiconductor layer having the first conductivity type such that a pn junction electrically isolates the body region from the substrate.

17. The semiconductor device of claim 15 , wherein the isolation region comprises an isolation layer that electrically isolates the body region from the substrate.

18. The semiconductor device of claim 15 , wherein the isolation trench further comprises a conductive material, and wherein the dielectric material is disposed between the conductive material and the body region.

19. The semiconductor device of claim 15 , wherein the channel region is non-linear.

20. The semiconductor device of claim 15 , wherein the gate electrode is electrically connected to a word line, the source region is electrically connected to a source line running parallel to the word line, and the emitter region is electrically connected directly to a bit line running transverse to the word line.

21. The semiconductor device of claim 15 , wherein the transistor forms part of a memory cell for storing information represented by a charge, wherein the charge is stored in the body region.

22. The semiconductor device of claim 21 , wherein the transistor is configured to adopt one of at least two states distinguishable by corresponding threshold voltages depending on the charge in the body region.

23. An integrated circuit including a semiconductor memory device comprising a plurality of memory cells, wherein each memory cell comprises a respective transistor, said transistor comprises:

a transistor body of a first conductivity type, wherein the transistor body is electrically isolated from transistor bodies of neighboring memory cells;

a drain area and a source area each having a second conductivity type, said drain area and source area are embedded in the transistor body on a first horizontal surface of said transistor body;

a gate structure having a gate dielectric layer and a gate electrode, wherein said gate structure is arranged between said drain area and said source area;

an emitter area of said first conductivity type, wherein said emitter area is operably associated with said drain area; and

at least one bit line and at least one source line, wherein said source area is connected to said source line, and said emitter area is connected directly to said bit line through a bit line contact.