Method and apparatus for reducing standby current in a dynamic random access memory during self refresh

1. A dynamic random access memory, comprising:

a first dynamic random access memory cell;

a second dynamic random access memory cell to be refreshed;

a sense amplifier; and

a control circuit configured to connect the sense amplifier to a first bit line associated with the first dynamic random access memory cell and to a second bit line associated with the second dynamic random access memory cell and to equalize bit line voltages and inputs of the sense amplifier to a bit line equalization voltage during a pre-conditioning time that is prior to a refresh time, wherein the control circuit is configured to isolate the first bit line from the sense amplifier and refresh the second dynamic random access memory cell during the refresh time.

2. The dynamic random access memory of claim 1 , comprising:

a first circuit coupled between the sense amplifier and the first dynamic random access memory cell; and

a second circuit coupled between the sense amplifier and the second dynamic random access memory cell.

3. The dynamic random access memory of claim 2 , wherein the first circuit is configured to isolate the sense amplifier from the first dynamic random access memory cell and the second circuit is configured to isolate the sense amplifier from the second dynamic random access memory cell.

4. The dynamic random access memory of claim 1 , wherein the control circuit is configured to connect the sense amplifier to the first bit line and isolate the sense amplifier from the second bit line in an idle time that is prior to the pre-conditioning time.

5. The dynamic random access memory of claim 1 , wherein the control circuit is configured to connect the first bit line to the sense amplifier and to equalize the bit line voltages and the inputs of the sense amplifier to the bit line equalization voltage during a post-conditioning time that follows the refresh time.

6. The dynamic random access memory of claim 5 , wherein the control circuit is configured to isolate the sense amplifier from the second bit line in an idle time that follows the post-conditioning time.

7. A dynamic random access memory, comprising:

a first segment of first dynamic random access memory cells including first bit lines;

a second segment of second dynamic random access memory cells including second bit lines;

sense amplifiers;

a first circuit configured to isolate the sense amplifiers from the first bit lines;

a second circuit configured to isolate the sense amplifiers from the second bit lines; and

a control circuit configured to connect the sense amplifiers via the first circuit to the first bit lines and via the second circuit to the second bit lines and to equalize bit line voltages and inputs of the sense amplifiers to a bit line equalization voltage during a pre-conditioning time that is prior to a refresh time, wherein the control circuit is configured to isolate the first bit lines from the sense amplifiers and to refresh the second segment of dynamic random access memory cells during the refresh time.

8. The dynamic random access memory of claim 7 , wherein the control circuit is configured to connect the sense amplifiers to the first bit lines via the first circuit and isolate the sense amplifiers from the second bit lines via the second circuit in an idle time that is prior to the pre-conditioning time.

9. The dynamic random access memory of claim 7 , wherein the control circuit is configured to connect the sense amplifiers to the first bit lines via the first circuit and to equalize the bit line voltages and the inputs of the sense amplifiers to the bit line equalization voltage during a post conditioning time that follows the refresh time.

10. A dynamic random access memory, comprising:

first dynamic random access memory cells;

second dynamic random access memory cells;

a sense amplifier;

a first pre-charge circuit configured to pre-charge first bit lines corresponding to the first dynamic random access memory cells;

a second pre-charge circuit configured to pre-charge second bit lines corresponding to the second dynamic random access memory cells;

a first isolation circuit configured to isolate the sense amplifier from the first pre-charge circuit;

a second isolation circuit configured to isolate the sense amplifier from the second pre-charge circuit; and

a control circuit configured to connect the sense amplifier to the first pre-charge circuit via the first isolation circuit and the second pre-charge circuit via the second isolation circuit and equalize bit line voltages and inputs of the sense amplifier to a bit line equalization voltage during a pre-conditioning time that is prior to a refresh time, wherein the control circuit is configured to isolate the first pre-charge circuit from the sense amplifier and to refresh the second dynamic random access memory cells during the refresh time.

11. The dynamic random access memory of claim 10 , wherein the control circuit is configured to connect the sense amplifier to the first pre-charge circuit via the first isolation circuit and isolate the sense amplifier from the second pre-charge circuit via the second isolation circuit in an idle time that is prior to the pre-conditioning time.

12. The dynamic random access memory of claim 10 , wherein the control circuit is configured to connect the sense amplifier to the first pre-charge circuit via the first isolation circuit and to equalize the bit line voltages and the inputs of the sense amplifier to the bit line equalization voltage during a post conditioning time that follows the refresh time.

13. A dynamic random access memory, comprising:

means for connecting sense amplifiers to first bit lines associated with first dynamic random access memory cells during a pre-conditioning time that is prior to a refresh time;

means for connecting the sense amplifiers to second bit lines associated with second dynamic random access memory cells during the pre-conditioning time;

means for equalizing bit line voltages and inputs of the sense amplifiers to a bit line equalization voltage during the pre-conditioning time;

means for isolating the first bit lines from the sense amplifiers during the refresh time; and

means for refreshing the second dynamic random access memory cells during the refresh time.

14. The dynamic random access memory of claim 13 , comprising:

means for isolating the sense amplifiers from the second bit lines in an idle time that is prior to the pre-conditioning time.

15. The dynamic random access memory of claim 13 , comprising:

means for connecting the sense amplifiers to the first bit lines during a post-conditioning time that follows the refresh time; and

means for equalizing the bit line voltages and the inputs of the sense amplifiers to the bit line equalization voltage during the post-conditioning time.

16. The dynamic random access memory of claim 15 , comprising:

means for isolating the sense amplifiers from the second bit lines in an idle time that follows the post-conditioning time.

17. A method for refreshing dynamic random access memory cells comprising:

connecting sense amplifiers to first bit lines associated with first dynamic random access memory cells during a pre-conditioning time that is prior to a refresh time;

connecting the sense amplifiers to second bit lines associated with second dynamic random access memory cells during the pre-conditioning time;

equalizing bit line voltages and inputs of the sense amplifiers to a bit line equalization voltage during the pre-conditioning time;

isolating the first bit lines from the sense amplifiers during the refresh time; and

refreshing the second dynamic random access memory cells during the refresh time.

18. The method of claim 17 , comprising:

isolating the sense amplifiers from the second bit lines in an idle time that is prior to the pre-conditioning time.

19. The method of claim 17 , comprising:

connecting the sense amplifiers to the first bit lines during a post-conditioning time that follows the refresh time; and

equalizing the bit line voltages and the inputs of the sense amplifiers to the bit line equalization voltage during the post-conditioning time.

20. The method of claim 19 , comprising:

isolating the sense amplifiers from the second bit lines in an idle time that follows the post-conditioning time.