Semiconductor memory device having a redundancy information memory directly connected to a redundancy control circuit

1. A semiconductor memory device, comprising:

a memory array having a plurality of memory cells;

a redundancy array having a plurality of memory cells;

a non-volatile redundancy information memory having a plurality of memory cells for storing redundancy information, wherein the memory cells in each column of the memory array are coupled to a same sense amplifier as at least one corresponding memory cell of the non-volatile redundancy information memory; and

a redundancy control unit for selecting either memory cells in the memory array or memory cells in the redundancy array, wherein the non-volatile redundancy information memory is connected directly to the redundancy control unit by means of at least one sense amplifier.

2. The semiconductor memory device according to claim 1 , wherein the memory cells in the memory array and the memory cells in the redundancy array are arranged in columns.

3. The semiconductor memory device according to claim 2 , wherein the number of memory cells in the non-volatile redundancy information memory is greater than or equal to the number of columns of memory cells in the memory array.

4. The semiconductor memory device according to claim 3 , wherein each memory cell in the non-volatile redundancy information memory is coupled to the redundancy control unit by means of a respective sense amplifier.

5. The semiconductor memory device according to claim 4 , wherein the non-volatile redundancy information memory is part of the memory array.

6. The semiconductor memory device according to claim 1 , wherein the redundancy control unit is coupled to control inputs of at least one bitline driver multiplexer and to control inputs of at least one sense amplifier multiplexer, wherein:

the at least one bitline driver multiplexer couples a data bus to either a bitline driver of the memory array or to a bitline driver of the redundancy array; and

the at least one sense amplifier multiplexer couples either a sense amplifier of the memory array or a sense amplifier of the redundancy array to the data bus.

7. The semiconductor memory device according to claim 1 , wherein at least the memory cells of one of the memory array, the redundancy array and the non-volatile redundancy information memory are nitride read only memory cells.

8. A method for operating a semiconductor memory device, the method comprising:

providing a memory array having a plurality of memory cells, a redundancy array having a plurality of memory cells, a non-volatile redundancy information memory having a plurality of memory cells for storing redundancy information, and a redundancy control unit;

receiving an address;

reading the redundancy information stored in the non-volatile redundancy information memory directly into the redundancy control unit by means of at least one sense amplifier; and

selecting either a memory cell in the memory array or a memory cell in the redundancy array for one of a read, write and erase operation by means of the redundancy control unit and depending on the redundancy information that corresponds to the address received; and

performing a memory operation comprising accessing the memory cell in the memory array with the at least one sense amplifier if the memory array is selected.

9. The method according to claim 8 , wherein in the step of reading the redundancy information, the redundancy information is read out of the memory cells of the non-volatile redundancy information memory in parallel by respective sense amplifiers.

10. The method according to claim 8 , further comprising transferring data between the selected memory cell and a data bus.

11. The method according to claim 10 , wherein reading the redundancy information stored in the non-volatile redundancy information memory directly into the redundancy control unit comprises transferring redundancy information to the redundancy control unit without accessing the data bus.

12. A semiconductor memory device, comprising:

a memory array having a plurality of memory cells;

a redundancy array having a plurality of memory cells;

a non-volatile redundancy information memory having a plurality of memory cells for storing redundancy information;

a data bus;

at least one sense amplifier, the at least one sense amplifier coupled to the memory array and the non-volatile redundancy information memory;

access circuitry coupled between the memory array and the data bus and also between the redundancy array and the data bus; and

a redundancy control unit coupled to the access circuitry, the redundancy control unit also being coupled to the non-volatile redundancy information memory through at least one line that is separate from the data bus.

13. The semiconductor memory device according to claim 12 , wherein the at least one sense amplifier is coupled between the non-volatile redundancy information memory and the redundancy control unit in series with the at least one line.

14. The semiconductor memory device according to claim 12 , wherein the access circuitry comprises a write driver multiplexer.

15. The semiconductor memory device according to claim 14 , wherein the access circuitry further comprises a sense amplifier multiplexer.

16. The semiconductor memory device according to claim 14 , further comprising:

a write driver coupled between the write driver multiplexer and the memory array; and

a redundant write driver coupled between the write driver multiplexer and the redundancy array.

17. The semiconductor memory device according to claim 12 , wherein the access circuitry comprises a sense amplifier multiplexer.

18. The semiconductor memory device according to claim 17 , further comprising a redundant sense amplifier coupled between the sense amplifier multiplexer and the redundancy array.

19. The semiconductor memory device according to claim 18 , wherein the at least one sense amplifier is coupled between the sense amplifier multiplexer and the memory array.

20. The semiconductor memory device according to claim 12 , wherein the memory array includes a plurality of nitride read only memory cells, the redundancy array includes a plurality of nitride read only memory cells, and the non-volatile redundancy information memory includes a plurality of nitride read only memory cells.