Memory having directed auto-refresh

1. A memory comprising:

at least two memory banks, each memory bank comprising an array of memory cells including rows and columns; and

a control circuit configured to simultaneously select a first of the at least two memory banks for a read or write operation and a second of the at least two memory banks for a directed auto-refresh,

wherein the control circuit comprises a bank address counter configured to provide a memory bank address for the second of the at least two memory banks, and

wherein the control circuit comprises an activate, auto-refresh, self-refresh, and bank selection circuit configured to provide a memory bank address for the first of the at least two memory banks.

2. The memory of claim 1 , wherein the control circuit comprises a directed auto-refresh memory bank selection circuit configured to select the second of the at least two memory banks.

3. A memory comprising:

at least two memory banks, each memory bank comprising an array of memory cells including rows and columns; and

a control circuit configured to simultaneously select a first of the at least two memory banks for a read or write operation and a second of the at least two memory banks for a directed auto-refresh,

wherein the control circuit is configured to block a directed auto-refresh of a memory bank if the memory bank is already active.

4. The memory of claim 3 , wherein the control circuit is configured to allow a directed auto-refresh of a memory bank with another memory bank active.

5. A memory comprising:

at least two memory banks, each memory bank comprising an array of memory cells including rows and columns;

an activate, auto-refresh, self-refresh, and bank selection circuit configured to provide a memory bank address for a first of the at least two memory banks for a read or write operation; and

a directed auto-refresh memory bank selection circuit configured to simultaneously select a second of the at least two memory banks for a directed auto-refresh,

wherein the directed auto-refresh memory bank selection circuit is configured to block a directed auto-refresh of a memory bank if the memory bank is already active.

6. The memory of claim 5 , further comprising:

a bank address counter configured to provide a memory bank address for the second of the at least two memory banks.

7. The memory of claim 5 , wherein the directed auto-refresh memory bank selection circuit is configured to allow a directed auto-refresh of a memory bank with another memory bank active.

8. The memory of claim 5 , wherein the memory comprises a dynamic random access memory.

9. A memory comprising:

at least two memory banks, each memory bank comprising an array of memory cells including rows and columns;

means for simultaneously selecting a first of the at least two memory banks for a read or write operation and a second of the at least two memory banks for a directed auto-refresh in a directed auto-refresh mode; and

means for blocking a directed auto-refresh of a memory bank if the memory bank is already active,

wherein the directed auto-refresh mode is configured to refresh memory cells at a first row address in each of the at least two memory banks before refreshing memory cells at a second row address in each of the at least two memory banks.

10. The memory of claim 9 , further comprising:

means for allowing a directed auto-refresh of a memory bank with another memory bank active.

11. The memory of claim 9 , wherein the memory comprises a dynamic random access memory.

12. A method for refreshing a memory, the method comprising:

receiving a first memory bank address for a directed auto-refresh of a first memory bank;

receiving a second memory bank address for a read or write operation of a second memory bank;

selecting the second memory bank;

determining whether the first memory bank is already active; and

simultaneously selecting the first memory bank with the second memory bank based on the determination.

13. The method of claim 12 , further comprising:

decoding the first memory bank address to provide a signal for selecting the first memory bank.

14. The method of claim 12 , wherein receiving the first memory bank address comprises receiving the first memory bank address through a dedicated two bit memory bank address bus.

15. A method for operating a dynamic random access memory, the method comprising:

configuring the memory to enable a directed auto-refresh mode;

receiving a first memory bank address for a directed auto-refresh of a first memory bank;

decoding the first memory bank address to provide a signal for selecting the first memory bank;

decoding a directed auto-refresh command to set a first latch to provide a first pulse;

providing a second pulse based on the signal for selecting the first memory bank and the first pulse;

setting a second latch in response to the second pulse to pass the signal for selecting the first memory bank; and

selecting the first memory bank based on the signal for selecting the first memory bank.

16. The method of claim 15 , further comprising:

receiving a second memory bank address for a read or write operation of a second memory bank; and

simultaneously selecting the second memory bank with the first memory bank.

17. The method of claim 15 , wherein decoding the directed auto-refresh command to set the first latch comprises decoding the directed auto-refresh command to set a first set/reset latch.

18. The method of claim 15 , wherein setting the second latch comprises setting a second set/reset latch.

19. The method of claim 15 , further comprising:

resetting the first latch in response to the second pulse.