Maintaining internal voltages of an integrated circuit in response to a clocked standby mode
View Patent ↗A method and circuit for controlling an output reference voltage generated by a reference voltage generator disposed on a memory device are provided. A signal for enabling a clocked standby mode of the memory device is received. If the signal indicates that the memory device is in the clocked standby mode, a first reference voltage is generated as the output reference voltage of the reference voltage generator using a first voltage. If the signal indicates that the memory device is not in the clocked standby mode, a second reference voltage is generated as the output reference voltage of the reference voltage generator using a second voltage.
1. A method for controlling an output reference voltage generated by a reference voltage generator disposed on a device, comprising:
receiving a signal for enabling a clocked standby mode of the device;
if the signal indicates that the device is in the clocked standby mode, generating a first reference voltage as the output reference voltage of the reference voltage generator; and
if the signal indicates that the device is not in the clocked standby mode, generating a second reference voltage as the output reference voltage of the reference voltage generator, wherein the first reference voltage is larger than the second reference voltage; and wherein:
a voltage generation circuit maintains an output voltage using the generated output reference voltage, the voltage generation circuit being selectively enabled or disabled by a clocked standby mode signal when the device is in the clocked standby mode, and
the first reference voltage compensates for a voltage drop in the output voltage generated by the voltage generation circuit resulting from selectively enabling and disabling the voltage generation circuit.
2. The method of claim 1 , wherein a clocked standby mode clock signal selectively enables and disables the reference voltage generator when the device is in the clocked standby mode.
3. The method of claim 1 , wherein the first reference voltage is larger than the second reference voltage.
4. The method of claim 1 , wherein the device is a memory device.
5. A device for controlling an output reference voltage generated by a reference voltage generator disposed on the device, comprising:
circuitry configured to:
receive a signal for enabling a clocked standby mode of the device;
if the signal indicates that the device is in the clocked standby mode, generate a first reference voltage as the output reference voltage of the reference voltage generator; and
if the signal indicates that the device is not in the clocked standby mode, generate a second reference voltage as the output reference voltage of the reference voltage generator, wherein the first reference voltage is larger than the second reference voltage; and wherein:
a voltage generation circuit maintains an output voltage using the generated output reference voltage, the voltage generation circuit being selectively enabled or disabled by a clocked standby mode signal when the device is in the clocked standby mode, and
the first reference voltage compensates for a voltage drop in the output voltage generated by the voltage generation circuit resulting from selectively enabling and disabling the voltage generation circuit.
6. The device of claim 5 , wherein a clocked standby mode clock signal selectively enables and disables the reference voltage generator when the device is in the clocked standby mode.
7. The device of claim 5 , wherein the first reference voltage is larger than the second reference voltage.
8. The device of claim 5 , wherein the first reference voltage is different from the second reference voltage.
9. The method of claim 1 , wherein the first reference voltage is different from the second reference voltage.