Method for searching for potential faults in a layout of an integrated circuit
View Patent ↗A layout comprises a plurality of elemental areas which define the shape and arrangement of patterns of an integrated circuit. A method for searching for potential faults in the layout begins with dividing the layout into sections. One of a number of predetermined classes is allocated to a section by means of allocation criteria. An evaluation criterion allocated to the class which was allocated to the section is then applied to the section in order to obtain an evaluation result. Each section is then identified as potentially faulted in dependence on the evaluation result.
1. A method for searching for potential faults of a layout of an integrated circuit, the layout comprising a plurality of elemental areas which define a shape and arrangement of patterns of the integrated circuit, the method comprising:
a) dividing the layout into sections;
b) allocating one of a number of predetermined classes to a section of the sections by means of an allocation criteria, wherein an evaluation criterion is allocated to each class;
c) applying the evaluation criterion allocated to the class which was allocated to the section in step b) to the section to obtain an evaluation result; and
d) identifying the section as potentially faulted section in dependence on the evaluation result.
2. The method as claimed in claim 1 , in which, in step b), the allocation is made by means of a logical combination of allocation criteria.
3. The method as claimed in claim 2 , in which step d) further comprises:
d1) determining a quality of the section from the evaluation results; and
d2) identifying the section as potentially faulted if the quality of the section is less than a predetermined minimum quality.
4. The method as claimed in claim 3 , in which, in step a), the layout is divided into sections of uniform circuit function.
5. The method as claimed in claim 3 , in which, in step a), the layout is divided in accordance with geometric criteria.
6. The method as claimed in claim 1 , further comprising allocating to at least one class a number of evaluation criteria, application of which in step c) provides a number of evaluation results, the identification in step d) made based on a logical combination of the evaluation results.
7. The method as claimed in claim 6 , in which step d) further comprises:
d1) determining a quality of the section on the basis of a logical combination of the evaluation results; and
d2) identifying the section as potentially faulted if the quality of the section is less than a predetermined minimum quality.
8. The method as claimed in claim 7 , in which, in step a), the layout is divided into sections of uniform circuit function.
9. The method as claimed in claim 7 , in which, in step a), the layout is divided in accordance with geometric criteria.
10. The method as claimed in claim 1 , in which step d) further comprises:
d1) determining a quality of the section from the evaluation results; and
d2) identifying the section as potentially faulted if the quality of the section is less than a predetermined minimum quality.
11. The method as claimed in claim 10 , in which, in step a), the layout is divided into sections of uniform circuit function.
12. The method as claimed in claim 10 , in which, in step a), the layout is divided in accordance with geometric criteria.
13. The method as claimed in claim 1 , in which steps b), c) and d) are applied to every section.
14. The method as claimed in claim 1 , in which, in step a), the layout is divided into sections of uniform circuit function.
15. The method as claimed in claim 1 , in which, in step a), the layout is divided in accordance with geometric criteria.
16. The method as claimed in claim 15 , in which a boundary between two sections is formed by extending a straight edge section beyond a concave corner adjoining the straight edge section.
17. The method as claimed in claim 1 , in which one of the number of predetermined classes is included in the group which comprises a class for gate electrodes, a class for contact areas for via conductors, a class for straight conductor pieces, a class for conductor piece kinks and a class for a conductor piece branch.
18. The method as claimed in claim 1 , in which an evaluation criterion is formed by a number of convex corners, adjoining a section, in an edge of an elemental area, a component of which the section is.
19. The method as claimed in claim 1 , in which an evaluation criterion is formed by a number of concave corners, adjoining a section, in an edge of an elemental area, a component of which the section is.
20. A method for correcting a layout of an integrated circuit, the layout comprising a plurality of elemental areas which define a shape and arrangement of patterns of the integrated circuit, the method comprising:
a) searching for potentially faulted sections of the layout, comprising;
i) dividing the layout into sections;
ii) allocating one of a number of predetermined classes to a section of the sections by means of an allocation criteria, wherein an evaluation criterion is allocated to each class;
iii) applying the evaluation criterion allocated to the class which was allocated to the section in step ii) to the section to obtain an evaluation result; and
iv) identifying the section as potentially faulted section in dependence on the evaluation result;
b) identifying a potentially faulted section as actually faulted by means of further criteria; and
c) correcting a section if it has been identified as actually faulted.