Memory having parity error correction
View Patent ↗A memory includes a sense amplifier segment and a plurality of word lines including a first transfer word line and a second transfer word line complementary to the first transfer word line. The memory includes a plurality of bit lines coupled to the sense amplifier segment and a memory cell located at each cross point of each word line and each bit line. The first transfer word line and the second transfer word line are adapted for simultaneously inverting data bit values stored in memory cells along a failed word line to correct a parity error during self refresh.
1. A memory comprising:
a sense amplifier segment;
a plurality of word lines including a first transfer word line and a second transfer word line complementary to the first transfer word line;
a plurality of bit lines coupled to the sense amplifier segment; and
a memory cell located at each cross point of each word line and each bit line,
wherein the first transfer word line and the second transfer word line are adapted for simultaneously inverting data bit values stored in memory cells along a failed word line to correct a parity error during self refresh.
2. The memory of claim 1 , wherein the inverted data bit values are stored in the memory cells along the failed word line.
3. The memory of claim 1 , wherein the first transfer word line and the second transfer word line are adapted to correct parity errors without knowing a location of a failed memory cell along the failed word line.
4. The memory device of claim 1 , wherein the memory is a dynamic random access memory.
5. A memory comprising:
a sense amplifier segment;
a plurality of word lines including a first transfer word line and a second transfer word line;
a plurality of bit lines coupled to the sense amplifier segment;
a memory cell located at each cross point of each word line and each bit line; and
a latch configured to indicate a failed word line,
wherein a memory cell located along the first transfer word line coupled to a first sense amplifier is electrically shorted to a memory cell located along the second transfer word line coupled to the sense amplifier for inverting data bit values stored in memory cells along the failed word line to correct a parity error during self refresh;, and
wherein the inverted data bit values are stored in the memory cells along the failed word line.
6. The memory of claim 5 , wherein the first transfer word line and the second transfer word line are adapted to correct parity errors without knowing a location of a failed memory cell along the failed word line.
7. The memory of claim 5 , wherein the plurality of word lines comprises true word lines and complement word lines.
8. The memory of claim 5 , wherein the plurality of bit lines comprises true bit lines and complement bit lines.
9. The memory of claim 5 , wherein the memory is a dynamic random access memory.
10. A memory comprising:
means for simultaneously inverting data bit values stored in memory cells along a failed word line to correct for a parity error during self refresh; and
means for storing the inverted data bit values in the memory cells along the failed word line.
11. The memory of claim 10 , further comprising:
means for indicating that the data bit values stored in the memory cells along the failed word line are inverted.
12. The memory of claim 10 , further comprising:
means for re-inverting the data bit values stored in the memory cells along the failed word line during a memory access to provide corrected data bit values.
13. A memory comprising:
a sense amplifier segment;
a plurality of word lines including a first transfer word line and a second transfer word line complementary to the first transfer word line;
a plurality of bit lines coupled to the sense amplifier segment;
a memory cell located at each cross point of each word line and each bit line; and
a latch,
wherein the first transfer word line and the second transfer word line are adapted for simultaneously inverting data bit values stored in memory cells along a failed word line to correct a parity error during self refresh,
wherein the inverted data bit values are stored in the memory cells along the failed word line, and
wherein the latch is configured to indicate the failed word line for re-inverting the inverted data bit values stored in memory cells along the failed word line in a data path during a memory access.
14. The memory of claim 13 , wherein the first transfer word line and the second transfer word line are adapted to correct parity errors without knowing a location of a failed memory cell along the failed word line.
15. The memory device of claim 13 , wherein the memory is a dynamic random access memory.
16. A memory comprising:
means for simultaneously inverting data bit values stored in memory cells along a failed word line to correct for a parity error during self refresh;
means for storing the inverted data bit values in the memory cells along the failed word line; and
a latch configured to indicate the failed word line for re-inverting the inverted data bit values stored in memory cells along the failed word line in a data path during a memory access.
17. The memory of claim 16 , further comprising:
means for re-inverting the data bit values stored in the memory cells along the failed word line during a memory access to provide corrected data bit values.