Method for patterning a semiconductor component
View Patent ↗In a method for patterning a semiconductor component a first cover layer is applied to a first region and a second region of a semiconductor component being arranged in a semiconductor substrate. The first region is different from the second region. The first cover layer is patterned using a photolithographic mask so that the first region is uncovered and the second region remains covered by the first cover layer. The first region is uncovered, a second cover layer is applied to the uncovered first region, and the first cover layer is removed so that the second region is uncovered. The uncovered second region is then doped.
1. A method for patterning a semiconductor component, comprising the steps of:
providing at least one gate stack on a semiconductor component;
applying a first cover layer to a first region and a second region of the semiconductor component being arranged in a semiconductor substrate;
said first region being adjacent to one side of said gate stack and said second region being adjacent to an opposite side of said gate stack;
patterning said first cover layer using a photolithographic mask so that said first region is uncovered and said second region remains covered by said first cover layer;
implanting a dopant material at a first angle into the semiconductor component in said uncovered first region;
applying a second cover layer to said uncovered first region;
removing said first cover layer by means of a selective etching process so that said second region is uncovered; and
implanting a dopant material at a second angle into the semiconductor component in said uncovered second region, the first angle and the second angle being different.
2. The method of claim 1 , comprising removing said first cover layer by a selective etching.
3. The method of claim 1 , comprising removing said photolithographic mask at the earliest after removing said first cover layer from said first region and before removing selectively said first cover layer from said second region.
4. The method of claim 1 , comprising, following the step of applying said second cover layer, uncovering said first cover layer by planarizing and receding said second cover layer.
5. The method of claim 1 , wherein at least one of said first cover layer or said second cover layer comprises at least one of polysilicon, polysilicon-germanium, silicon oxide, aluminum oxide, and silicate glass.
6. The method of claim 1 , comprising doping at least one of said first region and second region by means of ion implantation.
7. The method of claim 1 , comprising doping said first region by means of ion implementation at a first implantation angle with respect to a surface of said semiconductor substrate and doping said second region by means of ion implementation at a second implantation angle with respect to said surface of said semiconductor substrate; said first implementation angle being different to said second implementation angle.
8. The method of claim 7 , comprising doping said second region by means of multiple ion implantation at different second implantation angles.
9. The method of claim 1 , comprising arranging at least one vertical gate stack on said semiconductor component; said first region and said second region being horizontally adjacent to two opposite sides of said vertical gate stack.
10. The method of claim 1 , comprising applying a spacer to said uncovered second region and to said second cover layer in said first region.