Random access memory having voltage provided out of boosted supply voltage

1. A random access memory, comprising:

an array of single transistor memory cells; and

a voltage source configured to receive a negative word line voltage and a reference voltage and to provide an output voltage out of the negative word line voltage and based on the reference voltage, wherein the voltage source comprises:

a first transistor configured to receive the negative word line voltage and to pull the output voltage toward the negative word line voltage based on a comparison of the output voltage and the reference voltage.

2. The random access memory of claim 1 , wherein the voltage source comprises:

a comparator configured to receive the reference voltage and an input voltage based on feedback from the output voltage and to compare the reference voltage and the input voltage and provide a comparator output voltage that is based on the comparison of the reference voltage and the input voltage, wherein the first transistor is configured to receive the comparator output voltage and to regulate the output voltage based on the comparator output voltage.

3. The random access memory of claim 1 , wherein the voltage source comprises:

a second transistor configured to provide a current source to regulate the output voltage.

4. A random access memory, comprising:

an array of single transistor memory cells;

a voltage source configured to receive a boosted supply voltage and a reference voltage and to provide an output voltage out of the boosted supply voltage and based on the reference voltage, wherein the voltage source comprises:

a first comparator configured to receive the reference voltage and a first input voltage based on feedback from the output voltage and to compare the reference voltage and the first input voltage and provide a first comparator output voltage that is based on the comparison of the reference voltage and the first input voltage;

a first transistor configured to receive the boosted supply voltage and the first comparator output voltage and to regulate the output voltage based on the first comparator output voltage; and

a second transistor configured to provide a current source to regulate the output voltage.

5. A random access memory, comprising:

an array of single transistor memory cells;

a voltage source configured to receive a boosted supply voltage and a reference voltage and to provide an output voltage out of the boosted supply voltage and based on the reference voltage, wherein the voltage source comprises:

a first comparator configured to receive the reference voltage and a first input voltage based on feedback from the output voltage and to compare the reference voltage and the first input voltage and provide a first comparator output voltage that is based on the comparison of the reference voltage and the first input voltage;

a first transistor configured to receive the boosted supply voltage and the first comparator output voltage and to regulate the output voltage based on the first comparator output voltage;

a second comparator configured to receive the reference voltage and a second input voltage based on feedback from the output voltage and to compare the reference voltage and the second input voltage and provide a second comparator output voltage that is based on the comparison of the reference voltage and the second input voltage; and

a second transistor configured to receive the second comparator output voltage and to regulate the output voltage based on the second comparator output voltage.

6. A random access memory, comprising:

an array of random access memory cells;

a voltage source configured to receive a negative word line voltage and to provide an output voltage out of the negative word line voltage, wherein the voltage source comprises:

a first comparator configured to receive a first reference voltage and a first input voltage that is based on feedback from the output voltage and to compare the first reference voltage and the first input voltage and provide a first comparator output voltage;

a second comparator configured to receive a second reference voltage and a second input voltage that is based on feedback from the output voltage and to compare the second reference voltage and the second input voltage and provide a second comparator output voltage; and

a first transistor configured to receive the negative word line voltage and the first comparator output voltage and to pull the cutout voltage toward the negative word line voltage based on the first comparator output voltage, wherein the voltage source regulates the output voltage out of the negative word line voltage via the first comparator output voltage and the second comparator output voltage.

7. The random access memory of claim 6 , wherein the voltage source comprises:

a second transistor configured to receive a pull up voltage and the second comparator output voltage and to pull the output voltage toward the pull-up voltage based on the second comparator output voltage.

8. A random access memory, comprising:

an array of random access memory cells;

a voltage source configured to receive a boosted supply voltage and to provide an output voltage out of the boosted supply voltage, wherein the voltage source comprises:

a first comparator configured to receive a first reference voltage and a first input voltage that is based on feedback from the output voltage and to compare the first reference voltage and the first input voltage and provide a first comparator output voltage;

a second comparator configured to receive a second reference voltage and a second input voltage that is based on feedback from the output voltage and to compare the second reference voltage and the second input voltage and provide a second comparator output voltage, wherein the voltage source regulates the output voltage out of the boosted supply voltage via the first comparator output voltage and the second comparator output voltage;

a first transistor configured to receive the boosted supply voltage and the first comparator output voltage and to pull the output voltage toward the boosted supply voltage based on the first comparator output voltage; and

a second transistor configured to receive the second comparator output voltage and to pull the output voltage away from the boosted supply voltage based on the second comparator output voltage.

9. The random access memory of claim 6 , wherein the first reference voltage received at the first comparator and the second reference voltage received at the second comparator are substantially equal.

10. The random access memory of claim 6 , wherein the negative word line voltage received at the voltage source provides word line bias and the output voltage provides transistor well back bias.

11. A random access memory, comprising:

an array of random access memory cells, wherein each of the random access memory cells includes a transistor well configured to receive a back bias voltage;

word lines crossing random access memory cells in the array of random access memory cells, wherein each of the word lines is configured to receive a word line voltage; and

a voltage source configured to receive the word line voltage and regulate the back bias voltage out of the word line voltage, wherein the voltage source comprises:

a first comparator configured to receive a first reference voltage and a first input voltage that is based on the back bias voltage and to compare the first reference voltage and the first input voltage and provide a first comparator output voltage;

a first transistor configured to receive the word line voltage and the first comparator output voltage and to pull the back bias voltage toward the word line voltage based on the first comparator output voltage;

a second comparator configured to receive a second reference voltage and a second input voltage that is based on the back bias voltage and to compare the second reference voltage and the second input voltage and provide a second comparator output voltage; and

a second transistor configured to receive the second comparator output voltage and to pull the back bias voltage away from the word line voltage based on the second comparator output voltage.

12. The random access memory of claim 11 , wherein the first reference voltage received at the first comparator and the second reference voltage received at the second comparator are substantially equal.

13. The random access memory of claim 11 , wherein the back bias voltage regulated out of the word line voltage via the voltage source is a negative back bias voltage value and the word line voltage is a negative word line voltage value.

14. A random access memory, comprising:

means for storing data in an array of memory cells;

means for receiving a negative word line voltage and a reference voltage; and

means for regulating an output voltage out of the negative word line voltage and based on the reference voltage, comprising:

means for pulling the output voltage toward the negative word line voltage based on a comparison of the output voltage and the reference voltage.

15. The random access memory of claim 14 , wherein the means for regulating comprises:

means for providing a first input voltage based on the output voltage;

means for comparing the reference voltage and the first input voltage; and

means for providing a first comparison output voltage that is based on the comparison of the reference voltage and the first input voltage.

16. The random access memory of claim 15 , wherein the means for pulling the output voltage comprises:

means for pulling the output voltage toward the negative word line voltage based on the first comparison output voltage.

17. The random access memory of claim 16 , wherein the means for regulating comprises:

means for providing a current source to regulate the output voltage.

18. The random access memory of claim 16 , wherein the means for regulating comprises:

means for providing a second input voltage based on the output voltage;

means for comparing the reference voltage and the second input voltage;

means for providing a second comparison output voltage that is based on the comparison of the reference voltage and the second input voltage; and

means for pulling the output voltage toward a pull-up voltage based on the second comparison output voltage.

19. A random access memory, comprising:

means for storing data in an array of random access memory cells;

means for receiving a first reference voltage and a first input voltage that is based on feedback from an output voltage;

means for comparing the first reference voltage and the first input voltage to provide a first comparison output voltage;

means for receiving a second reference voltage and a second input voltage that is based on feedback from the output voltage;

means for comparing the second reference voltage and the second input voltage to provide a second comparison output voltage; and

means for regulating the output voltage out of a negative word line voltage via the first comparison output voltage and the second comparison output voltage, wherein the means for regulating comprises:

means for receiving the negative word line voltage and the first comparison output voltage and pulling the output voltage toward the negative word line voltage based on the first comparison output voltage.

20. The random access memory of claim 19 , wherein the means for regulating comprises:

means for pulling the output voltage away from the negative word line voltage based on the second comparison output voltage.

21. The random access memory of claim 19 , wherein the negative word line voltage provides word line bias and the output voltage provides transistor well back bias.

22. A method for providing a voltage in a random access memory, comprising:

receiving a negative word line voltage that provides word line bias in an array of random access memory cells;

receiving a reference voltage; and

regulating an output voltage that provides transistor well back bias in the array of random access memory cells out of the negative word line voltage and based on the reference voltage, comprising:

pulling the output voltage toward the negative word line voltage based on a comparison of the output voltage and the reference voltage.

23. The method of claim 22 , wherein regulating an output voltage comprises:

feeding back the output voltage to provide a first input voltage to a comparator;

comparing the reference voltage and the first input voltage; and

outputting a first comparator output voltage that is based on the comparison of the reference voltage and the first input voltage.

24. The method of claim 23 , wherein pulling the output voltage comprises:

pulling the output voltage toward the negative word line voltage based on the first comparator output voltage.

25. The method of claim 24 , wherein regulating an output voltage comprises:

sourcing a current to regulate the output voltage.

26. The method of claim 24 , wherein regulating an output voltage comprises:

feeding back the output voltage to provide a second input voltage;

comparing the reference voltage and the second input voltage;

providing a second comparator output voltage that is based on the comparison of the reference voltage and the second input voltage; and

pulling the output voltage toward a pull-up voltage based on the second comparator output voltage.

27. A method for providing a voltage in a random access memory, comprising:

receiving a negative word line voltage that provides word line bias in an array of random access memory cells;

receiving a first input voltage that is based on feedback from an output voltage;

comparing a first reference voltage and the first input voltage to provide a first comparison output voltage;

receiving a second input voltage that is based on feedback from the output voltage;

comparing a second reference voltage and the second input voltage to provide a second comparison output voltage;

regulating the output voltage that provides transistor well back bias in the array of random access memory cells out of the negative word line voltage via the first comparison output voltage and the second comparison output voltage, wherein regulating the output voltage comprises:

receiving the negative word line voltage and the first comparison output voltage; and,

pulling the output voltage toward the negative word line voltage based on the first comparison output voltage.

28. The method of claim 27 , wherein regulating the output voltage comprises:

pulling the output voltage away from the negative word line voltage based on the second comparison output voltage.

29. A method for providing a back bias voltage in a random access memory, comprising:

receiving a word line voltage in an array of random access memory cells;

receiving a first reference voltage and a first input voltage that is based on the back bias voltage at a first comparator;

comparing the first reference voltage and the first input voltage via the first comparator to provide a first comparator output voltage;

receiving the word line voltage and the first comparator output voltage at a first transistor;

pulling the back bias voltage toward the word line voltage based on the first comparator output voltage;

receiving a second reference voltage and a second input voltage that is based on the back bias voltage at a second comparator;

comparing the second reference voltage and the second input voltage via the second comparator to provide a second comparator output voltage;

receiving the second comparator output voltage at a second transistor; and

pulling the back bias voltage away from the word line voltage based on the second comparator output voltage.

30. The method of claim 29 , wherein the first reference voltage received at the first comparator and the second reference voltage received at the second comparator are substantially equal.

31. The method of claim 29 , wherein the back bias voltage regulated out of the word line voltage is a negative back bias voltage value and the word line voltage is a negative word line voltage value.