Method for fabricating a memory cell arrangement with a folded bit line arrangement and corresponding memory cell arrangement with a folded bit line arrangement

1. An integrated circuit having a memory cell arrangement with a folded bit line arrangement, comprising:

a plurality of active regions along a first direction in a semiconductor body; the active regions being surrounded by isolation trenches on all sides;

a plurality of parallel buried word lines along a second direction in the semiconductor body; the buried word lines running through the active regions and having an upper portion below a surface of the semiconductor body, where two of the buried word lines are spaced apart from one another and from the isolation trenches running through a respective active region, and the buried word lines being insulated from a channel region in the respective active region by a gate dielectric layer;

a source region between the two buried word lines;

a first drain region between one of the two buried word lines and an isolation trench portion;

a second drain region between the other of the two buried word lines and another isolation trench portion;

a plurality of parallel bit lines along a third direction at the surface of the semiconductor body; the bit lines running perpendicular to the second direction;

wherein a bit line makes contact with the source region;

a plurality of storage capacitors; a first and second storage capacitor of the plurality of storage capacitors being connected to the first and second drain regions, respectively;

wherein the first direction is diagonal to the second and third directions.

2. The integrated circuit of claim 1 , further comprising an insulation layer formed between the bit lines; and

a plurality of capacitor contacts formed in the insulation layer; wherein first and second capacitor contacts make contact with the first and second drain regions, respectively; and wherein the first and second storage capacitors are connected to the respective first and second drain regions via the respective first and second capacitor contacts.

3. The integrated circuit of claim 1 , wherein the plurality of bit lines are formed from a polysilicon layer in electrical contact with the source region, an overlying metal layer, and an overlying silicon nitride layer on a top side of the semiconductor body, and wherein silicon nitride sidewall spacers are formed on sidewalls of the bit lines.

4. The integrated circuit of claim 3 , further comprising gates for peripheral elements of the memory cell arrangement formed from the layers of the bit lines.

5. The integrated circuit of claim 1 , further comprising word line trenches running through the semiconductor body, wherein each word line trench comprises at least one buried word line.

6. The integrated circuit of claim 5 , wherein the buried word lines comprise a metallic filling arranged above a gate dielectric layer in the word line trench.

7. The integrated circuit of claim 6 , further comprising a respective insulative layer on top of the metallic filling for closing off each respective word line trench.

8. An integrated circuit formed on a substrate, the integrated circuit comprising:

a plurality of active regions formed in the substrate as line segments oriented in a first direction; the active regions being surrounded by isolation trenches on all sides;

a plurality of buried word lines running in parallel along a second direction, wherein each active region is intersected by two buried word lines, thereby defining a source region and two drain regions at an upper end of the respective active region, the source region being located between the two buried wordlines, and the two drain regions being located at the respective sides of the two buried wordlines being opposite relative to the source region;

a plurality of bit lines running in a third direction perpendicular to the second direction and being connected to corresponding source regions;

a plurality of storage capacitors; each storage capacitor being connected to a corresponding drain region;

wherein the first direction is diagonal to the second and third directions.

9. An integrated circuit formed on a substrate, the integrated circuit comprising:

a plurality of active regions formed in the substrate as line segments oriented in a first direction;

a plurality of buried word lines having an upper portion below a surface of the semiconductor body, the buried word lines running in parallel along a second direction, wherein an active region is intersected by two buried word lines, thereby defining a source region and two drain regions at an upper end of the respective active region, the source region being located between the two buried word lines, and the two drain regions being located at the respective sides of the two buried word lines being opposite relative to the source region;

a plurality of bit lines running in a third direction perpendicular to the second direction and being connected to corresponding source regions;

a plurality of storage capacitors; each storage capacitor being connected to a corresponding drain region;

wherein the first direction is diagonal to the second and third directions.