Method of transferring signals between a memory device and a memory controller

1. A method of transferring signals between a memory device and a memory controller, the method comprising:

configuring the memory device to transfer data signals to the memory controller at a first rate; and

configuring the memory device to transfer at least one of command signals and address signals to the memory controller at a second rate, wherein the second rate is slower than the first rate, wherein the command, address and data signals are transferred in frames; and wherein a frame contains a first subframe containing data signals and a second subframe containing the at least one of command and address signals.

2. The method of claim 1 , wherein the second rate is half the first rate.

3. The method of claim 1 , wherein the memory device transfers a predefined command signal to the memory controller at the second rate and wherein the predefined command signal identifies a command sequence code selected from a predefined group of command sequence codes, each command sequence code identifying a predefined sequence of commands.

4. The method of claim 3 , wherein a number of command sequence codes in the predefined group of command sequence codes is less than a total number of possible command sequences capable of being transferred between the memory device and the memory controller.

5. The method of claim 3 , wherein transferring the selected command sequence code comprises transferring an error correction code.

6. The method of claim 1 , wherein:

within the first subframe, a data bit is transferred at each rising edge and each falling edge of a clock signal; and

within the second subframe, one command or address bit, respectively, is transferred at each cycle of the clock signal, each cycle of the clock signal comprising a rising edge and a falling edge of the clock signal.

7. The method of claim 1 , wherein:

the second subframe comprises a command sequence code,

the command sequence code is selected from a predefined group of command sequence codes, and

each command sequence code identifies a predefined sequence of commands.

8. The method of claim 3 , wherein transferring the selected command sequence code comprises transferring each bit of the command sequence code twice.

9. A microelectronic device for a data storage system, comprising:

an input/output section for communicating command signals, address signals and data signals,

wherein the input/output section is configured for communicating data signals at a first rate and for communicating at least one of the command signals and address signals at a second rate, wherein the second rate is slower than the first rate, and wherein the microelectronic device is selected from one of a memory device and a memory controller, wherein the input/output section is configured such that:

the input/output section transmits and/or receives the command, address and data signals in frames; and

the input/output section transmits and/or receives a frame containing a first subframe comprising data signals and a second subframe comprising at least one of the command and address signals.

10. The microelectronic device of claim 9 , wherein the input/output section is configured such that the second rate is half the first rate.

11. The microelectronic device of claim 9 , wherein

the input/output section is configured for transmitting and/or receiving a command sequence code selected from a predefined group of command sequence codes each identifying a predefined sequence of commands.

12. The microelectronic device of claim 11 , wherein a number of command sequence codes comprised in the group of command sequence codes is less than a total number of possible command sequences capable of being communicated by the input/output section.

13. The microelectronic device of claim 9 , wherein the input/output section is designed such that:

within the first subframe, the input/output section transfers one data bit at each rising and each falling edge of a clock signal; and

within the second subframe, the input/output section transfers one command or address bit, respectively, at each cycle of the clock signal, each cycle of the clock signal comprising a rising edge and a falling edge.

14. The microelectronic device of claim 9 , wherein the second subframe comprises a command sequence code selected from a predefined group of command sequence codes each identifying a predefined sequence of commands.

15. The microelectronic device of claim 9 , wherein the input/output section is configured for transmitting or receiving, respectively, each bit of the command sequence code twice.

16. The microelectronic device of claim 9 , wherein the input/output section is configured for transmitting or receiving, respectively, an error correction code for each command sequence code.

17. A system, comprising the microelectronic device of claim 9 and a plurality of electrical components, the plurality of electrical components being at least one of structurally and functionally related.

18. The system of claim 17 , wherein at least one of the plurality of electrical components is a memory controller.

19. A method of transferring signals between a memory device and a memory controller, the method comprising:

configuring the memory controller to transfer data signals to the memory device at a first rate; and

configuring the memory controller to transfer at least one of command signals and address signals to the memory device at a second rate, wherein the second rate is slower than the first rate, wherein the command, address and data signals are transferred in frames; and wherein a frame contains a first subframe containing data signals and a second subframe containing the at least one of command and address signals.