Low power phase change memory cell with large read signal

1. A memory cell comprising:

a first electrode having a top surface;

a second electrode having a bottom surface parallel to the top surface of the first electrode;

phase-change material comprising a first portion contacting the top surface of the first electrode, a second portion contacting the bottom surface of the second electrode, and a third portion between the first portion and the second portion; and

a dielectric material laterally surrounding and directly contacting the first portion, the second portion, and the third portion,

wherein a width of the third portion is less than a width of the first portion and a width of the second portion, the first, second, and third portion each comprising a same chalcogen free material compound.

2. The memory cell of claim 1 , wherein the width of the first portion is approximately equal to the width of the second portion.

3. The memory cell of claim 1 , wherein the phase-change material forms an “I” shape.

4. A memory cell comprising:

a first electrode having a top surface;

a second electrode having a bottom surface parallel to the top surface of the first electrode; and

phase-change material comprising a first portion contacting the top surface of the first electrode, a second portion contacting the bottom surface of the second electrode, and a third portion between the first portion and the second portion,

wherein a width of the third portion is less than a width of the first portion and a width of the second portion, the first, second, and third portion each comprising a same chalcogen free material compound,

wherein the phase-change material forms an hourglass shape such that a sidewall of the phase-change material extending between the first electrode and the second electrode is curved.

5. The memory cell of claim 4 , wherein the width of the first portion is approximately equal to the width of the second portion.

6. A memory device comprising:

a write pulse generator for generating a write pulse signal;

a sense amplifier for sensing a read signal;

a distribution circuit; and

a plurality of phase-change memory cells each comprising phase-change material, each memory cell capable of defining at least a first state and a second state,

wherein the phase-change material for each memory cell includes a first portion contacting a top surface of a first electrode, a second portion contacting a bottom surface of a second electrode, and a third portion between the first portion and the second portion, the top surface of the first electrode parallel to the bottom surface of the second electrode,

wherein a minimum width of the third portion is less than one half of a maximum first width of the first portion and a maximum second width of the second portion, the first, second, and third portion each comprising a same chalcogen free material compound, and

wherein a dielectric material laterally surrounds and directly contacts the first portion, the second portion, and the third portion.

7. The memory device of claim 6 , wherein a maximum width of the third portion is less than a minimum first width of the first portion and a minimum second width of the second portion.

8. The memory device of claim 6 , wherein a maximum width of the third portion is less than the maximum first width of the first portion and the maximum second width of the second portion.

9. The memory device of claim 6 , wherein the minimum width of the third portion is less than a minimum first width of the first portion and a minimum second width of the second portion.

10. The memory device of claim 6 , wherein the maximum first width of the first portion is approximately equal to the maximum second width of the second portion.

11. The memory device of claim 6 , wherein the phase-change material for each memory cell forms an “I” shape.

12. A memory device comprising:

a write pulse generator for generating a write pulse signal;

a sense amplifier for sensing a read signal;

a distribution circuit; and

a plurality of phase-change memory cells each comprising phase-change material, each memory cell capable of defining at least a first state and a second state,

wherein the phase-change material for each memory cell includes a first portion contacting a top surface of a first electrode, a second portion contacting a bottom surface of a second electrode, and a third portion between the first portion and the second portion, the top surface of the first electrode parallel to the bottom surface of the second electrode,

wherein a minimum width of the third portion is less than one half of a maximum first width of the first portion and a maximum second width of the second portion, the first, second, and third portion each comprising a same chalcogen free material compound, and

wherein the phase-change material for each memory cell forms an hourglass shape such that a sidewall of the phase-change material extending between the first electrode and the second electrode is curved.

13. The memory device of claim 12 , wherein a maximum width of the third portion is less than a minimum first width of the first portion and a minimum second width of the second portion.

14. The memory device of claim 12 , wherein a maximum width of the third portion is less than the maximum first width of the first portion and the maximum second width of the second portion.

15. The memory device of claim 12 , wherein the minimum width of the third portion is less than a minimum first width of the first portion and a minimum second width of the second portion.

16. The memory device of claim 12 , wherein the maximum first width of the first portion is approximately equal to the maximum second width of the second portion.

17. An integrated circuit including a memory cell comprising:

a first electrode having a top surface;

a second electrode having a bottom surface parallel to the top surface of the first electrode;

resistance changing material comprising a first portion contacting the top surface of the first electrode, a second portion contacting the bottom surface of the second electrode, and a third portion between the first portion and the second portion; and

a dielectric material laterally surrounding and directly contacting the first portion, the second portion, and the third portion,

wherein a width of the third portion is less than one half of a width of the first portion and a width of the second portion, the first, second, and third portion each comprising a same chalcogen free material compound.

18. The integrated circuit of claim 17 , wherein the width of the first portion is approximately equal to the width of the second portion.

19. The integrated circuit of claim 17 , wherein the resistance changing material forms an “I” shape.

20. The integrated circuit of claim 17 , wherein the resistance changing material comprises phase-change material.

21. An integrated circuit including a memory cell comprising:

a first electrode having a top surface;

a second electrode having a bottom surface parallel to the top surface of the first electrode; and

resistance changing material comprising a first portion contacting the top surface of the first electrode, a second portion contacting the bottom surface of the second electrode, and a third portion between the first portion and the second portion,

wherein a width of the third portion is less than one half of a width of the first portion and a width of the second portion, the first, second, and third portion each comprising a same chalcogen free material compound, and

wherein the resistance changing material forms an hourglass shape such that a sidewall of the resistance changing material extending between the first electrode and the second electrode is curved.

22. The integrated circuit of claim 21 , wherein the width of the first portion is approximately equal to the width of the second portion.

23. The integrated circuit of claim 21 , wherein the resistance changing material comprises phase-change material.