Output circuit that turns off one of a first circuit and a second circuit

1. An integrated circuit having an output circuit, comprising:

a first circuit configured to provide a first output signal;

a second circuit configured to provide a second output signal; and

a third circuit configured to receive a third output signal that is based on the first output signal and the second output signal and to provide enable signals that turn on one of the first circuit and the second circuit and turn off the other of the first circuit and the second circuit based on the third output signal that is updated via the turned on one of the first circuit and the second circuit.

2. The integrated circuit having the output circuit of claim 1 , wherein the third circuit delays the third output signal and provides a delayed third output signal that is used to provide the enable signals.

3. The integrated circuit having the output circuit of claim 1 , wherein the third circuit latches in the third output signal and provides a latched third output signal that is used to provide the enable signals.

4. The integrated circuit having the output circuit of claim 1 , comprising:

a fourth circuit configured to receive the first output signal and the second output signal and to provide driver signals based on the first output signal and the second output signal; and

a fifth circuit configured to update the third output signal based on the driver signals.

5. The integrated circuit having the output circuit of claim 4 , comprising:

a sixth circuit configured to maintain the third output signal based on the driver signals and the third output signal; and

a seventh circuit configured to bias an input of the turned on one of the first circuit and the second circuit based on the driver signals and the third output signal.

6. The integrated circuit having the output circuit of claim 1 , comprising:

a fourth circuit configured to latch in the third output signal.

7. An integrated circuit including a random access memory, comprising:

a first circuit configured to provide a first output signal;

a second circuit configured to provide a second output signal;

means for enabling one of the first circuit and the second circuit to activate the one of the first circuit and the second circuit based on a third output signal;

means for disabling the other one of the first circuit and the second circuit to deactivate the other one of the first circuit and the second circuit based on the third output signal; and

means for updating the third output signal via the enabled one of the first circuit and the second circuit.

8. The integrated circuit including the random access memory of claim 7 , wherein the means for enabling and the means for disabling comprises:

means for delaying the third output signal to provide a delayed third output signal;

means for enabling one of the first circuit and the second circuit based on the delayed third output signal; and

means for disabling the other one of the first circuit and the second circuit based on the delayed third output signal.

9. The integrated circuit including the random access memory of claim 7 , wherein the means for enabling and the means for disabling comprises:

means for latching the third output signal to provide a latched third output signal;

means for enabling one of the first circuit and the second circuit based on the latched third output signal; and

means for disabling the other one of the first circuit and the second circuit based on the latched third output signal.

10. The integrated circuit including the random access memory of claim 7 , comprising:

means for maintaining the third output signal based on the third output signal; and

means for biasing an input of the enabled one of the first circuit and the second circuit based on the third output signal.

11. A method for outputting signals, comprising:

providing a first output signal from a first circuit;

providing a second output signal from a second circuit;

enabling one of the first circuit and the second circuit to activate the one of the first circuit and the second circuit based on a third output signal;

disabling the other one of the first circuit and the second circuit to deactivate the other one of the first circuit and the second circuit based on the third output signal; and

updating the third output signal based on the first output signal and the second output signal via the enabled one of the first circuit and the second circuit.

12. The method of claim 11 , wherein enabling and disabling comprises:

delaying the third output signal to provide a delayed third output signal;

enabling one of the first circuit and the second circuit based on the delayed third output signal; and

disabling the other one of the first circuit and the second circuit based on the delayed third output signal.

13. The method of claim 11 , wherein enabling and disabling comprises:

latching the third output signal to provide a latched third output signal;

enabling one of the first circuit and the second circuit based on the latched third output signal; and

disabling the other one of the first circuit and the second circuit based on the latched third output signal.

14. The method of claim 11 , comprising:

recharging the third output signal based on the third output signal; and

biasing an input of the enabled one of the first circuit and the second circuit based on the third output signal.