Test mode method and apparatus for internal memory timing signals

1. A method of testing internal signals of a memory for timing marginalities which may result in unstable operation, comprising:

delaying internal address signals of the memory by an amount great enough so that data cannot be validly written to and read from memory locations which are accessed by address signals having timing marginalities which are delayed but small enough so that data can be validly written to and read from memory locations which are accessed by address signals not having such timing marginalities which are delayed;

writing to and reading data from said memory locations which are accessed by delayed address signals; and

determining whether the data read from any memory location does not correspond with the data written to such memory location.

2. The method of claim 1 wherein if the data read from any memory location does not correspond to the data written to such memory location, determining the identity of the delayed address signal which caused such lack of correspondence to occur.

3. The method of claim 1 wherein row address signals for memory locations are delayed independently of column address signals for such memory locations, and wherein data is written to and read from the memory after the row address signal corresponding to a given memory location is delayed and also after the column address signal corresponding to the memory location is delayed.

4. The method of claim 1 wherein data written to memory locations accessed by delayed address signals comprises both high bits and low bits.

5. The method of claim 1 wherein control signals including those performing the functions of row address strobe, column address strobe, and write or read enable are independently delayed, and data is written to and read from the memory after each such signal is delayed to test the timing marginality of the control signals.

6. A method of testing internal signals of a memory for timing marginalities which may result in unstable operation, comprising:

delaying internal address signals of the memory by an amount great enough so that data cannot be validly written to and read from memory locations which are accessed by address signals having timing marginalities which are delayed but small enough so that data can be validly written to and read from memory locations which are accessed by address signals not having such timing marginalities which are delayed;

writing to and reading data from said memory locations which are accessed by delayed address signals;

comparing the read data from each said memory location with the data written to such memory location; and

if the data read from any memory location does not correspond with the data written to said memory location, determining the identity of the delayed address signal which caused such lack of correspondence to occur.

7. The method of claim 6 wherein row address signals for memory locations are delayed independently of column address signals for such memory locations, and wherein data is written to and read from the memory after the row address signal corresponding to a given memory location is delayed and also after the column address signal corresponding to the memory location is delayed.

8. The method of claim 6 wherein data written to memory locations accessed by delayed address signals comprises both high bits and low bits.

9. The method of claim 6 wherein control signals including those performing the functions of row address strobe, column address strobe, and write or read enable are independently delayed, and data is written to and read from the memory after each such signal is delayed to test the timing marginality of the control signals.

10. The method of claim 6 wherein address signals corresponding to each memory location of the memory are tested.

11. An apparatus for testing internal signals of a memory for timing marginalities which may result in unstable operation, comprising:

a plurality of delay lines operably connected so as to delay internal address signals of the memory by an amount great enough so that data cannot be validly written to and read from memory locations which are accessed by address signals having timing marginalities which are delayed but small enough so that data can be validly written to and read from memory locations which are accessed by address signals not having such timing marginalities which are delayed, whereby timing marginalities of internal address signals can be characterized.

12. The apparatus of claim 11 wherein a plurality of additional delay lines are operably connected so as to delay control signals including those performing the functions of row address strobe, column address strobe and write or read enable, whereby timing marginalities of such control signals may be characterized.

13. The apparatus of claim 12 further comprising a register for storing data written to memory locations accessed by address signals having delay lines operably connected therewith.

14. The apparatus of claim 13 further comprising a comparator for comparing stored data with data read from memory locations accessed by address signals having delay lines operably connected therewith.

15. The apparatus of claim 14 wherein said delay lines comprise programmable delay lines.

16. A test mode apparatus for a memory which data is written to and read from comprising a plurality of delay lines operably connected so as to delay internal address signals of the memory resulting in delayed address signals, a controller for controlling the sequence of accessing memory locations with delayed address signals, a register for storing data written to memory locations and a comparator for comparing said data written to memory locations with data read from such memory locations.

17. The apparatus of claim 16 further comprising a plurality of additional delay lines operably connected so as to delay control signals including those performing the functions of row address strobe, column address strobe and read or write enable.

18. The apparatus of claim 15 wherein said controller determines whether a high or low bit is to be written to individual memory locations.

19. The apparatus of claim 16 wherein the delay lines are programmable.

20. The apparatus of claim 19 wherein the controller determines the amount of the delay inserted by the programmable delay lines.

21. An apparatus for testing internal signals of a memory for timing marginalities which may result in unstable operation, comprising:

means for delaying internal address signals of the memory by an amount great enough so that data cannot be validly written to and read from memory locations which are accessed by address signals having timing marginalities which are delayed but small enough so that data can be validly written to and read from memory locations which are accessed by address signals not having such timing marginalities which are delayed;

means for writing to and reading data from said memory locations which are accessed by delayed address signals; and

means for determining whether the data read from any memory location does not correspond with the data written to such memory location.

22. The apparatus of claim 21 further comprising means for determining the identity of the delayed address signal which caused a lack of correspondence of the data written to any memory location with the data read from the memory location.

23. The apparatus of claim 21 further comprising means for delaying row address signals for memory locations independently of column address signals for such memory locations.

24. The apparatus of claim 21 further comprising means for writing both high and low bits to memory locations accessed by delayed address signals.

25. The method of claim 21 further comprising means for independently delaying respective control signals including those performing the functions of row address strobe, column address strobe and write or read enable.