Random access memory including circuit to compress comparison results

1. A random access memory comprising:

an array of memory cells configured to store memory cell data;

a first circuit configured to compare test data and memory cell data to obtain comparison results; and

a second circuit configured to compress the comparison results and store the compressed comparison results, wherein the second circuit is configured to receive each of the comparison results and compare each of the comparison results to a stored value to obtain one of the compressed comparison results, wherein the stored value is updated to the one of the compressed comparison results.

2. The random access memory of claim 1 , comprising:

a third circuit configured to read memory cell data from memory cells in the array of memory cells at a first data rate and to output the compressed comparison results via the second circuit at a second data rate, wherein the first data rate is faster than the second data rate.

3. A random access memory comprising:

an array of memory cells configured to store memory cell data;

a first circuit configured to compare test data and memory cell data to obtain comparison results;

a second circuit configured to compress the comparison results and store the compressed comparison results; and

a control circuit configured to read memory cell data from memory cells in the array of memory cells at a first data rate to provide the memory cell data to the first circuit and configured to output the compressed comparison results via the second circuit at a second data rate, wherein the first data rate is faster than the second data rate, wherein the control circuit is configured to read memory cells via first word lines in a row redundancy group at the first data rate and to read memory cells via a last word line in the row redundancy group at the second data rate to obtain the compressed comparison results.

4. The random access memory of claim 3 , wherein the first data rate is at a first clock rate and the second data rate is at a second clock rate that is substantially one half of the first clock rate.

5. A random access memory comprising an array of memory cells configured to have rows of memory cells;

a first circuit configured to read memory cell data from each of the rows of memory cells in the array of memory cells;

a second circuit configured to receive the memory cell data from each of the rows of memory cells and to compare the memory cell data from each of the rows of memory cells to test data and provide row comparison results; and

a third circuit configured to receive each of the row comparison results and compare each of the row comparison results to stored values to obtain compressed results, wherein the stored values are updated to the compressed results and the first circuit is configured to output stored values via the third circuit.

6. The random access memory of claim 5 , wherein the third circuit comprises;

a fourth circuit configured to compare each of the row comparison results to stored values via a logic function to obtain compressed results; and

a fifth circuit configured to update the stored values to the compressed results.

7. The random access memory of claim 6 , wherein the fourth circuit is configured to compare each of the row comparison results to stored values via an OR gate function and the fifth circuit comprises a register configured to update the stored values to the compressed values and store the updated stored values.

8. The random access memory of claim 7 , comprising bit lines that cross the array of memory cells and each of the bit lines provides memory cell data from memory cells in one column of the array of memory cells, wherein the third circuit comprises OR gates and registers and each of the bit lines provides data from memory cells in one column to a corresponding one of the OR gates that supplies an OR gate result to a corresponding one of the registers.

9. The random access memory of claim 7 , wherein the third circuit comprises registers that are addressed via a column address to update the stored values to the compressed results and to output the stored values.

10. A random access memory comprising means for storing memory cell data in an array of memory cells;

means for comparing the memory cell data and test data to obtain comparison results;

means for compressing the comparison results; and

means for storing the compressed comparison results, wherein the means for compressing the comparison results comprises:

means for comparing each of the comparison results to a stored value to obtain one of the compressed comparison results.

11. The random access memory of claim 10 , comprising:

means for reading memory cell data from memory cells in the array of memory cells at a first data rate; and

means for outputting the compressed comparison results at a second data rate that is slower than the first data rate.

12. The random access memory of claim 11 , wherein the means for reading memory cell data comprises:

means for reading first memory cell data from the memory cells at the first data rate; and

means for reading second memory cell data from the memory cells at the second data rate.

13. The random access memory of claim 10 , wherein the means for storing the compressed comparison results comprises:

means for updating the stored value to the one of the compressed comparison results.

14. A method for testing a random access memory, comprising:

storing data in the random access memory;

comparing the stored data and test data to obtain comparison results via a first circuit in the random access memory;

compressing the comparison results via a second circuit in the random access memory;

storing the compressed comparison results in the random access memory;

reading first stored data in the random access memory at a first data rate to provide the first stored data to the first circuit;

outputting the compressed comparison results via the second circuit at a second data rate that is slower than the first data rate;

reading the first stored data via first word lines in a row redundancy group at the first data rate; and

reading second stored data via a last word line in the row redundancy group at the second data rate to obtain the compressed comparison results.

15. A method for testing a random access memory, comprising:

storing data in the random access memory;

comparing the stored data and test data to obtain comparison results via a first circuit in the random access memory;

compressing the comparison results via a second circuit in the random access memory; and

storing the compressed comparison results in the random access memory, wherein compressing the comparison results comprises:

comparing each of the comparison results to a stored value to obtain one of the compressed comparison results.

16. The method of claim 15 , wherein storing the compressed comparison results comprises:

updating the stored value to the one of the compressed comparison results.

17. A method for testing a random access memory, comprising:

storing data in rows of memory cells in the random access memory;

reading stored data from one of the rows of memory cells;

comparing the stored data from the one of the rows of memory cells to test data to obtain row comparison results via a first circuit in the random access memory;

comparing the row comparison results to register values to obtain compressed results via a second circuit in the random access memory;

updating the register values to the compressed results; and

outputting the register values from the random access memory.

18. The method of claim 17 , wherein comparing the row comparison results comprises comparing the row comparison results to the register values via a logic function to obtain the compressed results.

19. The method of claim 17 , wherein comparing the row comparison results comprises comparing the row comparison results to the register values via an OR gate function.

20. The method of claim 17 , wherein reading stored data from one of the rows of memory cells comprises reading stored data from one of the rows of memory cells at a first data rate, and wherein outputting the register values comprises outputting the register values at a second data rate that is slower than the first data rate.

21. The method of claim 17 , comprising:

reading stored data via first word lines in a row redundancy group at a first data rate; and reading stored data via a last word line in the row redundancy group at a second data rate that is slower than the first data rate.