Semiconductor having structure with openings
View Patent ↗A process for producing an insulation structure with openings of a low aspect ratio is disclosed. In one embodiment, a dopant is introduced into the insulation structure with a concentration which on average increases or decreases in the vertical direction from a pre-processed semiconductor surface, the openings are formed in a dry-etching step and the aspect ratio of the openings is reduced by increasing the basic surface area of the openings using a subsequent wet-chemical etching step.
1. A process for manufacturing an integrated circuit on a pre-processed substrate comprising:
providing the pre-processed substrate with a structure arranged on the substrate;
producing a capping layer on the structure and removing the capping layer in regions where openings are to be formed;
removing the structure in the regions where the openings are to be formed;
wherein at least one dopant is introduced into the structure, with the concentration of the at least one dopant varying substantially continuously vertically from the surface of the pre-processed semiconductor substrate toward the capping layer and on average increasing or decreasing from the semiconductor substrate vertically toward the capping layer;
carrying out at least one dry-etching process; and
carrying out at least one subsequent wet-chemical etching process until sidewalls of the openings are formed substantially perpendicular to the surface of the pre-processed substrate.
2. The process as claimed in claim 1 , wherein the structure is made from polysilicon, the dopant is boron, the boron is introduced into the structure with a concentration which increases continuously from the surface of the pre-processed semiconductor substrate vertically toward the capping layer, and the wet-chemical etching step is carried out using at least nitric acid as etching solution.
3. The process as claimed in claim 1 , wherein the at least one dopant is introduced into the structure with a concentration which decreases continuously from the surface of the pre-processed semiconductor substrate vertically toward the capping layer.
4. The process as claimed in claim 3 , wherein the structure is made from polysilicon, the dopant is phosphorus and the wet-chemical etching step is carried out using at least nitric acid as etching solution.
5. The process as claimed in claim 1 , wherein Boron or Phosphorus or a combination thereof is introduced into the structure as dopant.
6. The process as claimed in claim 5 , wherein the structure is formed from silicon oxide or an oxide of silicon-germanium.
7. The process as claimed in claim 6 , wherein the wet-chemical etching process is carried out using dilute hydrofluoric acid as etching solution.
8. The process as claimed in claim 1 , further comprising producing first capacitor electrodes,
removing the structure to form free standing pillars of the first capacitor electrodes,
providing a capacitor dielectric and a second capacitor electrode on the first capacitor electrode.
9. The process as claimed in claim 8 , wherein the structure is made from polysilicon, the dopant is boron, the boron is introduced into the structure with a concentration which increases continuously from the surface of the pre-processed semiconductor substrate vertically toward the capping layer, and the wet-chemical etching step is carried out using at least nitric acid as etching solution.
10. The process as claimed in claim 8 , wherein the at least one dopant is introduced into the structure with a concentration which decreases continuously from the surface of the pre-processed semiconductor substrate vertically toward the capping layer.
11. The process as claimed in claim 8 , wherein the structure is made from polysilicon, the dopant is phosphorus and the wet-chemical etching step is carried out using at least nitric acid as etching solution.
12. The process as claimed in claim 8 , wherein Boron or Phosphorus or a combination thereof is introduced into the structure as dopant.
13. The process as claimed in claim 12 , wherein the structure is formed from silicon oxide or an oxide of silicon-germanium.
14. The process as claimed in claim 13 , wherein the wet-chemical etching process is carried out using dilute hydrofluoric acid as etching solution.
15. The process of claim 1 , further comprising filling the openings with a conductive material.
16. The process as claimed in claim 15 , wherein the structure is made from polysilicon, the dopant is boron, the boron is introduced into the structure with a concentration which increases continuously from the surface of the pre-processed semiconductor substrate vertically toward the capping layer, and the wet-chemical etching step is carried out using at least nitric acid as etching solution.
17. The process as claimed in claim 15 , wherein the at least one dopant is introduced into the structure with a concentration which decreases continuously from the surface of the pre-processed semiconductor substrate vertically toward the capping layer.
18. A process for manufacturing an integrated circuit on a pre-processed substrate comprising:
providing the pre-processed substrate with a structure arranged on the substrate;
producing a capping layer on the structure and removing the capping layer in regions where openings are to be formed;
removing the structure in the regions where the openings are to be formed;
wherein at least on dopant is introduced into the structure, with the concentration of the at least one dopant varying substantially continuously vertically from the surface of the pre-processed semiconductor substrate toward the capping layer and on average increasing or decreasing from the semiconductor substrate vertically toward the capping layer;
carrying out at least one dry-etching process; and
carrying out at least one subsequent wet-chemical etching process to reduce a taper of sidewalls of the openings.