Voltage monitoring test mode and test adapter
View Patent ↗A testing system has a processor, a module and at least one manufactured semiconductor device. The processor is configured to send and receive testing signals. The module is electrically coupled to the processor. The at least one manufactured semiconductor device is mounted on the module, and the semiconductor device has a plurality of pins at least one of which is a non-functional pin. The system is configured to provide the processor access to the semiconductor device. An external device monitors voltage at the non-functional pin of the semiconductor device.
1. A tester apparatus comprising:
a memory module;
a plurality of semiconductor random access memory devices coupled to the memory module, wherein each of the semiconductor random access memory devices have a non-functional pin;
the memory module further including connection lines coupled to the not-connected pin of each of the plurality of semiconductor random access memory devices such that voltage at each of the non-functional pins may be monitored at the connection lines of the memory module; and
a test pad, wherein each of the connection lines are configured to couple the non-functional pins of each of the plurality of semiconductor random access memory devices to the test pad.
2. The tester apparatus of claim 1 , wherein the test pad is configured such that voltage at each of the non-functional pins may be alternately monitored at the test pad.
3. A memory testing system comprising:
a processor configured to send and receive testing signals;
an adapter card coupled to the processor and configured to exchange signals with the processor;
a memory module coupled to the adapter card and configured to exchange signals with the adapter card;
a plurality of semiconductor memory devices mounted on the memory module, the semiconductor memory devices each having a plurality of functional pins and at least one non-functional pin; and
a test pad on the adapter card and coupled to the non-functional pin of each of the semiconductor memory devices for monitoring the voltage at the non-functional pins.
4. The memory testing system of claim 3 , wherein the adapter card and memory module further comprise connection lines coupling the non-functional pins of each of the plurality of semiconductor memory devices to the test pad.
5. The memory testing system of claim 4 , wherein the processor controls each of the plurality of semiconductor memory devices such that the voltage at the non-functional pins may be made selectively available at the test pad.
6. A method of testing a semiconductor memory device, the method comprising:
providing an adapter card;
coupling a memory module to the adapter card such that it is electrically coupled therewith;
mounting a plurality of semiconductor memory devices on the memory module, the semiconductor memory devices each having a plurality of pins at least one of which is a non-functional pin;
running an application test on the plurality of semiconductor memory devices, including driving some of the plurality of pins, but not driving the non-functional pin; and
monitoring voltage at a test pad on the adapter card, the test pad being coupled to the non-functional pin of each of the semiconductor memory devices.
7. The method of claim 6 , further comprising selectively enabling one of the plurality of semiconductor memory devices such that the voltage monitored at the test pad is the voltage of the non-functional pin on the selected semiconductor memory device.