Method and apparatus for selectively accessing and configuring individual chips of a semi-conductor wafer

1. A method of testing and individually configuring a plurality of chips of a wafer comprising:

(a) identifying said plurality of chips of said wafer for testing;

(b) coupling said identified chips to a wafer test system, wherein said system issues commands to test and configure said plurality of identified chips;

(c) assigning an identification to each of said identified chips and storing said assigned identification within a corresponding register of that chip in response to said identified chips receiving identification commands from said wafer test system;

(d) selecting an identified chip; and

(e) determining at least one parameter value for said selected chip and individually accessing said selected chip based on said assigned identification and storing each determined parameter value in the corresponding chip register to configure that chip in response to said identified chips receiving selection and parameter commands from said wafer test system, wherein at least two of said chips include different parameter values.

2. The method of claim 1 , wherein step (c) further includes:

(c.1) disabling power to said identified chips;

(c.2) enabling power to one of said identified chips;

(c.3) assigning an identification to said enabled chip and storing said assigned identification within said corresponding chip register; and

(c.4) selectively specifying a subsequent chip for assignment of said identification;

wherein steps (c.2)-(c.4) are repeated until each identified chip has been assigned an identification.

3. The method of claim 1 , wherein step (e) further includes:

(e.1) selecting a parameter of said chip and determining a value for said selected parameter;

(e.2) individually accessing said selected chip based on said assigned identification and storing said determined value for said selected parameter in a corresponding chip register;

(e.3) performing a functional test on said chip with said stored parameter value and evaluating test results; and

(e.4) identifying a subsequent parameter of said chip for determination in response to said test results being acceptable;

wherein steps (e.1)-(e.4) are repeated for each of said at least one parameter of said chip.

4. The method of claim 1 , wherein said plurality of chips each include a test interface, and step (c) further includes:

(c.1) receiving and processing said identification commands via said test interface to store said assigned identification within said corresponding chip register.

5. The method of claim 1 , wherein said plurality of chips each include a test interface, and step (e) further includes:

(e.1) receiving and processing said selection and parameter commands via said test interface to store each determined parameter value in said corresponding chip register of said selected identified chip.

6. The method of claim 1 , wherein each said chip includes a DRAM chip.

7. A system for testing and individually configuring a plurality of chips of a wafer comprising:

test means for issuing commands to test and configure said plurality of chips including:

test identification means for identifying and engaging said plurality of chips for testing;

assignment means for providing identification commands to said plurality of identified chips to assign an identification to each of those chips;

parameter select means for selecting an identified chip and determining at least one parameter value for said selected chip; and

parameter storage means for individually accessing said selected chip based on said assigned identification and providing selection and parameter commands to said identified chips to store said at least one parameter value for said selected chip; and

test interface means disposed on each said chip and including:

identification means to process said identification commands and store said assigned identification within a corresponding register of that chip; and

parameter means to process said selection and parameter commands and store each determined parameter value in the corresponding chip register to configure that chip, wherein at least two of said chips include different parameter values.

8. The system of claim 7 , wherein said assignment means includes:

disable means for disabling power to said identified chips;

selection means for selecting an identified chip for assignment of said identification;

enable means for enabling power to said selected chip; and

identification storage means for assigning an identification to said enabled chip and providing said identification command to said enabled chip to store said assigned identification within said corresponding chip register.

9. The system of claim 7 , wherein:

said parameter select means selects a parameter of said selected chip and determines a value for said selected parameter;

said parameter storage means individually accesses said selected chip based on said assigned identification; and

said parameter means stores said determined value for said selected parameter in said corresponding chip register and includes:

functional test means for performing a functional test on said chip with said stored parameter value, wherein said parameter select means identifies a subsequent parameter of that chip for determination in response to said test results being acceptable.

10. The system of claim 7 , wherein each said chip includes a DRAM chip.

11. A system for testing and individually configuring a plurality of chips of a wafer comprising:

a test system to issue commands to test and configure said plurality of chips including:

a test identification module to identify and engage said plurality of chips for testing;

an assignment module to provide identification commands to said plurality of identified chips to assign an identification to each of those chips;

a parameter select module to select an identified chip and determine at least one parameter value for said selected chip; and

a parameter storage module to individually access said selected chip based on said assigned identification and provide selection and parameter commands to said identified chips to store said at least one parameter value for said selected chip; and

a test interface disposed on each chip of said plurality of identified chips and including:

an identification module to process said identification commands and store said assigned identification within a corresponding register of the chip on which the test interface is disposed; and

a parameter module to process said selection and parameter commands and store each determined parameter value in a corresponding chip register to configure the chip on which the test interface is disposed, wherein at least two of said plurality of identified chips include different parameter values.

12. The system of claim 11 , wherein said assignment module includes:

a disable module to disable power to said identified chips;

a selection module to select an identified chip for assignment of said identification;

an enable module to enable power to said selected chip; and

an identification storage module to assign an identification to said enabled chip and provide said identification command to said enabled chip to store said assigned identification within said corresponding chip register.

13. The system of claim 11 , wherein:

said parameter select module selects a parameter of said selected chip and determines a value for said selected parameter;

said parameter storage module individually accesses said selected chip based on said assigned identification; and

said parameter module stores said determined value for said selected parameter in the corresponding chip register and includes:

a functional test module to perform a functional test on said chip with said stored parameter value, wherein said parameter select module identifies a subsequent parameter of that chip for determination in response to said test results being acceptable.

14. The system of claim 11 , wherein each said chip includes a DRAM chip.