Sense amplifier for eliminating leakage current due to bit line shorts

1. A sense amplifier for a memory comprising:

a transistor configured to be switched with a column select line to pass a bit line equalization voltage;

an array equalize device coupled to the transistor for receiving the bit line equalization voltage;

a sense amplifier equalize device;

a multiplexer coupled between the sense amplifier equalize device and the array equalize device; and

a cross-coupled amplifier latch coupled to the sense amplifier equalize device.

2. The sense amplifier of claim 1 , wherein the transistor comprises a p-channel field effect transistor.

3. The sense amplifier of claim 1 , wherein the sense amplifier equalize device is configured to be controlled based on a logical AND of a left array equalize device control signal and a right array equalize device control signal.

4. The sense amplifier of claim 1 , wherein the sense amplifier equalize. device comprises a bit line true to bit line complement equalize device.

5. The sense amplifier of claim 1 , wherein the sense amplifier equalize device comprises a bit line to bit line equalization voltage equalize device.

6. The sense amplifier of claim 1 , wherein the sense amplifier equalize device comprises a bit line true to bit line complement equalize device and a bit line to bit line equalization voltage equalize device.

7. The sense amplifier of claim 1 , wherein the array equalize device comprises a bit line true to bit line complement equalize device.

8. The sense amplifier of claim 1 , wherein the array equalize device comprises a bit line to bit line equalization voltage equalize device.

9. The sense amplifier of claim 1 , wherein the array equalize device comprises a bit line true to bit line complement equalize device and a bit line to bit line equalization voltage equalize device.

10. The sense amplifier of claim 1 , wherein the multiplexer is configured to be shut down during a standby state to isolate the cross-coupled amplifier latch from a memory array.

11. A sense amplifier for a memory comprising:

means for limiting a leakage current in a sense amplifier, the means for limiting controlled by a column select line;

means for equalizing a memory array voltage, the means for equalizing the memory array voltage coupled to the means for limiting;

means for equalizing a sense amplifier voltage;

means for isolating the means for equalizing the memory array voltage from the means for equalizing the sense amplifier voltage; and

means for sensing a memory cell voltage, the means for sensing coupled to the means for equalizing the sense amplifier voltage.

12. A method for operating a memory, the method comprising:

switching off a bit line equalization voltage to a first array equalize device for a first sense amplifier for a fail column during a standby state;

switching on the bit line equalization voltage to a second array equalize device for a second sense amplifier for a good column during the standby state; and

switching on the bit line equalization voltage to the first array equalize device for the fail column during an active state.

13. The method of claim 12 , further comprising:

enabling the first array equalize device during the standby state;

enabling a sense amplifier equalize device during the standby state;

disabling the first array equalize device during the active state; and

disabling the sense amplifier equalize device during the active state.

14. The method of claim 13 , further comprising:

disabling a multiplexer coupled between the first array equalize device and the sense amplifier equalize device during the standby state; and

enabling the multiplexer during the active state.

15. The method of claim 12 , further comprising:

driving a word line for a fail master word line to a logic low word line driver voltage during the standby state; and

driving the word line for the fail master word line to a negative word line low voltage during the active state.