Patent Assignment
Reel/Frame 023773/0457
Assignment of Assignor's Interest
Recorded: 2010-01-13
Received: 2010-01-13
Pages: 398
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2006-04-25
Assignee
QIMONDA AG
GUSTAV-HEINEMANN-RING 212, MUNICH, DEX, 81739, GERMANY
Covered Properties
(100)
Method for Producing an Electrically Conductive Contact
Application:
10/893,561 →
Circuit Element Having a First Layer of an Electrically Insulating Substrate Material and Method for Manufacturing a Circuit Element
Application:
10/857,635 →
Method for Fabricating a Photomask for an Integrated Circuit and Corresponding Photomask
Application:
10/736,775 →
Dynamic Memory Cell and Method of Manufacturing Same
Application:
10/733,043 →
Multi-Level Driver Stage
Application:
10/690,001 →
Memory Module with a Heat Dissipation Means
Application:
10/682,649 →
Method for Fabricating a Vertical Transistor, and Semiconductor Memory Cell Having a Trench Capacitor and an Associated Vertical Selection Transistor
Application:
10/626,956 →
Apparatus and Method for Calibrating Signals
Application:
10/618,056 →
Vertical Transistor, and a Method for Producing a Vertical Transistor
Application:
10/615,567 →
Method for Manufacturing a Buried Strap Contact in a Memory Cell
Application:
10/607,033 →
Method for Fabricating Microstructures and Arrangement of Microstructures
Application:
10/606,069 →
Method for Structuring a Lithography Mask
Application:
10/465,103 →
Circuit Element Having a First Layer Composed of an Electrically Insulating Substrate Material, a Method for Producing a Circuit Element, Bispyridinium Compounds and Their Use in Circuit Elements
Application:
10/600,750 →
Method for Eliminating Phase Conflict Centers in Alternating Phase Masks, and Method for Producing Alternating Phase Masks
Application:
10/455,764 →
Vertical 8F2 Cell Dram with Active Area Self-Aligned to Bit Line
Application:
10/447,065 →
Method for Producing a Mask Set for Lithography Including at Least One Mask and Methods for Imaging Structures of a Predetermined Layout into a Common Exposure Plane
Application:
10/439,193 →
Method for Testing an Electronic Component; Computer Program Product, Computer Readable Medium, and Computer Embodying the Method; and Method for Downloading the Program Embodying the Method
Application:
10/431,900 →
Method for Numerically Simulating an Electrical Circuit
Application:
10/422,580 →
Method for Compensating for Scatter/Reflection Effects in Particle Beam Lithography
Application:
10/408,806 →
Electronic Component with a Semiconductor Chip, Method of Producing an Electronic Component and a Panel with a Plurality of Electronic Components
Application:
10/396,841 →
Ferroelectric Memory Integrated Circuit with Improved Reliability
Application:
10/248,861 →
Method for Fabricating a P-Channel Field-Effect Transistor on a Semiconductor Substrate
Application:
10/372,989 →
Method for Forming a Hard Mask in a Layer on a Planar Device
Application:
10/370,857 →
Method for Generating Test Signals for an Integrated Circuit and Test Logic Unit
Application:
10/368,330 →
Integrated Memory and Method for Operating an Integrated Memory
Application:
10/368,081 →
Addressing Device for Selecting Regular and Redundant Elements
Application:
10/364,014 →
Memory Module with Improved Electrical Properties
Application:
10/360,456 →
Method of Checking Electrical Connections Between a Memory Module and a Semiconductor Memory Chip
Application:
10/356,921 →
Photolithographic Mask
Application:
10/353,463 →
Chemical Mechanical Polishing (Cmp) Process Using Fixed Abrasive Pads
Application:
10/353,733 →
Method for Producing a Cavity in a Monocrystalline Silicon Substrate and a Semiconductor Component Having a Cavity in a Monocrystalline Silicon Substrate with an Epitaxial Covering Layer
Application:
10/348,150 →
Memory Cell Having a Thin Insulation Collar and Memory Module
Application:
10/348,148 →
Digital Memory Circuit Having a Plurality of Memory Banks
Application:
10/342,901 →
Resist for Forming a Structure for Aligning an Electron or Ion Beam and Technique for Forming the Structure
Application:
10/340,987 →
Method for Processing a Substrate to Form a Structure
Application:
10/340,047 →
Contact Base with Detachable Contacts for Making Electrical Contact with an Electronic Component, in Particular a Multipin Electronic Component, and Module Carrier
Application:
10/340,464 →
Method and Logic/Memory Module for Correcting the Duty Cycle of at Least One Control/Reference Signal
Application:
10/340,046 →
Method for Storing Data in a Memory Device with the Possibility of Access to Redundant Memory Cells
Application:
10/339,031 →
Photomask and Method of Structuring a Photoresist by Double Exposure with Imaging Auxiliary Structures and Different Exposure Tools
Application:
10/331,641 →
Process Facility Having at Least Two Physical Units Each Having a Reduced Density of Contaminating Particles with Respect to the Surroundings
Application:
10/330,444 →
Integrated Circuit Having a Connection Pad for Stipulating One of a Plurality of Organization Forms, and Method for Operating the Circuit
Application:
10/324,432 →
Method for Activating Fuse Units in Electronic Circuit Device
Application:
10/325,100 →
Memory Unit and Branched Command/Address Bus Architecture Between a Memory Register and a Plurality of Memory Units
Application:
10/325,250 →
Electronic Device and Leadframe and Methods for Producing the Electronic Device and the Leadframe
Application:
10/325,251 →
Integrated Memory Having a Precharge Circuit for Precharging a Bit Line
Application:
10/325,349 →
Method for Trench Etching
Application:
10/321,185 →
Contact Pin for Testing Microelectronic Components Having Substantially Spherical Contacts
Application:
10/320,127 →
Method for Operating a Semiconductor Memory, and Semiconductor Memory
Application:
10/317,972 →
Method for Fabricating an Integrated Semiconductor Circuit
Application:
10/310,397 →
Method for Driving Memory Cells of a Dynamic Semiconductor Memory and Circuit Configuration
Application:
10/310,930 →
Layer Arrangement, Memory Cell, Memory Cell Arrangement and Method for Producing a Layer Arrangement
Application:
10/314,049 →
Semiconductor Chip, Fabrication Method, and Device for Fabricating a Semiconductor Chip
Application:
10/306,438 →
Leadframe of a Conductive Material and Component with a Leadframe of a Conductive Material
Application:
10/306,184 →
Integrated Memory and Method of Repairing an Integrated Memory
Application:
10/304,135 →
Field Effect Transistor and Fabrication Method
Application:
10/304,134 →
Process for Chemically Mechanically Polishing Wafers
Application:
10/304,131 →
Array of Synchronized Memory Modules
Application:
10/302,805 →
Device for Supplying Control Signals to Memory Units, and a Memory Unit Adapted Thereto
Application:
10/302,214 →
Method and Semiconductor Wafer Configuration for Producing an Alignment Mark for Semiconductor Wafers
Application:
10/301,393 →
Floating Gate Field-Effect Transistor
Application:
10/302,615 →
Semiconductor Memory Module with Low Current Consumption
Application:
10/301,398 →
Semiconductor Component
Application:
10/301,368 →
Integrated Circuit Having a Programmable Element and Method of Operating the Circuit
Application:
10/301,090 →
Semiconductor Device with Deep Trench Isolation and Method of Manufacturing Same
Application:
10/299,269 →
Memory, Processor System and Method for Performing Write Operations on a Memory Region
Application:
10/299,750 →
Reflection Mask and Method for Fabricating the Reflection Mask
Application:
10/298,429 →
Device and Method for Associating Information Concerning Memory Cells of a Memory with an External Memory
Application:
10/298,970 →
Process for Producing a Component Module
Application:
10/298,772 →
Sige Vertical Gate Contact for Gate Conductor Post Etch Treatment
Application:
10/298,717 →
Method for Connection of Circuit Units
Application:
10/298,837 →
Signal Distribution to a Plurality of Circuit Units
Application:
10/295,710 →
Circuit Device Having a Fuse
Application:
10/293,923 →
Fabrication Method for an Interconnect on a Substrate
Application:
10/292,621 →
Sub-Resolution Sized Assist Features
Application:
10/292,169 →
Reflection Mask for Euv-Lithography and Method for Fabricating the Reflection Mask
Application:
10/292,866 →
Method and Apparatus for Finding a Fault in a Signal Path on a Printed Circuit Board
Application:
10/292,847 →
Circuit for Setting a Signal Propagation Time for a Signal on a Signal Line and Method for Ascertaining Timing Parameters
Application:
10/291,069 →
Method for Fabricating a Mask for Semiconductor Structures
Application:
10/291,070 →
Memory Device and Method of Accessing a Memory Device
Application:
10/290,365 →
Method for Precharging Memory Cells of a Dynamic Semiconductor Memory During Power-Up and Semiconductor Memory
Application:
10/289,913 →
Integrated Circuit Having a Test Circuit and Method of Decoupling a Test Circuit in an Integrated Circuit
Application:
10/289,826 →
Method for Reconfiguring a Memory
Application:
10/288,911 →
Line Configuration for Bit Lines for Contact-Connecting at Least One Memory Cell, Semiconductor Component with a Line Configuration and Method for Fabricating a Line Configuration
Application:
10/288,387 →
Integrated Memory, and a Method of Operating an Integrated Memory
Application:
10/287,501 →
Method for Producing an Electronic Component Having a Plurality of Chips That Are Stacked One Above the Other and Contact-Connected to One Another
Application:
10/285,924 →
Configuration for Minimizing the Neel Interaction Between Two Ferromagnetic Layers on Both Sides of a Non-Ferromagnetic Separating Layer
Application:
10/284,775 →
Interconnect Structure for an Integrated Circuit and Corresponding Fabrication Method
Application:
10/285,090 →
Method and Apparatus for Refreshing Memory Cells
Application:
10/284,806 →
Configuration for Data Transmission in a Semiconductor Memory System, and Relevant Data Transmission Method
Application:
10/284,773 →
Process for Producing a Semiconductor Chip
Application:
10/284,649 →
Device for Accessing Registered Circuit Units
Application:
10/284,774 →
Method for Reducing the Contact Resistance in Organic Field-Effect Transistors by Applying a Reactive Intermediate Layer Which Dopes the Organic Semiconductor Layer Region-Selectively in the Contact Region
Application:
10/285,049 →
Method for Processing Data Representing Parameters Relating to a Plurality of Components of an Electrical Circuit, Computer Readable Storage Medium and Data Processing System Containing Computer-Executable Instructions for Performing the Method
Application:
10/285,051 →
Process for Silylating Photoresists in the Uv Range
Application:
10/285,050 →
Process for Structuring a Photoresist by Uv at Less Than 160 Nm and Then Aromatic and/or Alicyclic Amplification
Application:
10/285,052 →
Charge Trapping Memory Cell, Method for Fabricating It, and Semiconductor Memory Device
Application:
10/283,857 →
Method and Device for Reducing the Contact Resistance in Organic Field-Effect Transistors by Embedding Nanoparticles to Produce Field Boosting
Application:
10/283,883 →
Floating Gate Memory Cell, Method for Fabricating It, and Semiconductor Memory Device
Application:
10/283,913 →
Dynamic Memory Device and Method for Controlling Such a Device
Application:
10/283,992 →
Fabrication Method and Apparatus for Fabricating a Spatial Structure in a Semiconductor Substrate
Application:
10/281,697 →